I would use the XCR3128XL, unfortunately, the only available packages are 100 pin and 144 pin, which gives you far more I/O than you need for your application. You may well be able to squeeze other needed glue logic into it though, so maybe not a big issue. The things easily make 100 MHz, so speed is not an issue. The I/O pins are also tolerant of 5 volt inputs.
The one downfall with the Coolrunner family is that individual I/O pins can not be made open collector, in other Xilinx CPLD's, this can be achieved. The Coolrunner family was originally a Philips device. They sold the thing to Xilinx. They use very little current, which is a bonus. NB: the core is designed to run from 3.3 volts. 4 Volts MAX. Careful of some of the later families, they require 1.8 volts on the core. And the I/O for those is not tolerant to 5 volts! As someone pointed out, the JTAG programmer uses 5 tri state buffers (74hc125 * 2 ) Connected via the parallel port of a WINDOWS PC. Easily made. These things are so fast that often you need to filter the inputs via a 3 stage shift register, and look across the last two bits to get a "clean" signal. (triggers on noise that only very good CRO's can see!) Cheers Harry -----Original Message----- From: [email protected] [mailto:[email protected]]on Behalf Of Dmitry Sent: Thursday, November 21, 2002 10:27 PM To: [email protected] Subject: Re: [Mspgcc-users] off-topic, but nowhere to ask :) Stefan, well, I checked the web site. thanks. I actually cannot get through so quickly. But I have to make a preliminary decision within a couple of hours. The thing I need is a 32 bit counter (28 actually, but 32 lloks better :) which is up/down counter and which counts as: input is two (50% duty cycly) sequences. One sequence shifted against other by pi/2. Depending on a sign of shift the counter should cont either up or down. Then I have to transmitt a counter value to cpu via 8 bit bus. However, the counter should continue work during lathing and transmission. Also, I need an output wich shows up or down counting, input for latch select, latch address and counter clear. Which fpga will you recommend for this and which one will work? Thanks, ~d On Thursday 21 November 2002 12:56, Stefan Wimmer wrote: > From: Dmitry [mailto:[email protected]] > > > has anybody experience in > > 1. cascading 74f579 (8 bit bidirectional counter or are there > > more bits > > up/down counters which work up to 10 MHz?) > > 2. interfacing it (5v vcc) with msp430 via latch > > Do you know about the Coolrunner CPLDs from Xilinx (developed by Philips > IIRC)? > http://www.xilinx.com/products/cr2/overview.htm > The software to configure the CPLDs (ISE WebPack) can be downloaded for > free. > http://www.xilinx.com/ise/ise_promo/ise5_cr2.htm > > They'd solve both 1. and 2. with the additional benefit that their power > consumption fit the MSP more than a 74Fxxx. > > HTH, > Stefan > > > ------------------------------------------------------- > This sf.net email is sponsored by:ThinkGeek > Welcome to geek heaven. > http://thinkgeek.com/sf > _______________________________________________ > Mspgcc-users mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/mspgcc-users -- /******************************************************************** ("`-''-/").___..--''"`-._ (\ Dimmy the Wild UA1ACZ `6_ 6 ) `-. ( ).`-.__.`) Enterprise Information Sys (_Y_.)' ._ ) `._ `. ``-..-' Nevsky prospekt, 20 / 44 _..`--'_..-_/ /--'_.' ,' Saint Petersburg, Russia (il),-'' (li),' ((!.-' +7 (812) 3468202, 5585314 ********************************************************************/ ------------------------------------------------------- This sf.net email is sponsored by:ThinkGeek Welcome to geek heaven. http://thinkgeek.com/sf _______________________________________________ Mspgcc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/mspgcc-users
