10 MHz is very fast - but it's slow for an interferometer output.
~d On Thursday 21 November 2002 15:22, David Brown wrote: > I would image this sort of thing would turn up quite often as examples in > fpga/cpld design tools. If not, a quick search of comp.arch.fpga archives > should probably give you some hints - it is probably also the best place to > ask for suggestions as to which type of programmable logic chip would be > the easiest. But now that I know it is a quadrature encoder you are using, > I agree with other posters that programable logic is the easiest way to go, > especially for such a high speed. 10 MHz is very fast for an encoder - a > high accuracy 5000 pulse encoder would have to be spinning at 60,000 rpm to > get that sort of frequency. Are you sure you have the correct frequency > here? > > > Sounds like quadrature encoding, a couple of flipflops can determine the > > direction, plus you need 32 ffs for the counter chain, and 32 for the > > buffer > > > latch, you are at 64 + 2 flipflops without considering any other logic so > > the 128 macrocell device would be a good fit. You will probably need to > > brush up a little on VHDL, I'm not sure if the latest free tools support > > schematic capture for Xilinx. But the VHDL isn't difficult, although for > > a first timer I would imagine the entire design flow might initially be a > > bit > > > mysterious. > > > > Cheers > > Harry > > > > > > > > > > -----Original Message----- > > From: [email protected] > > [mailto:[email protected]]on Behalf Of Dmitry > > Sent: Thursday, November 21, 2002 10:27 PM > > To: [email protected] > > Subject: Re: [Mspgcc-users] off-topic, but nowhere to ask :) > > > > Stefan, > > > > well, I checked the web site. thanks. > > I actually cannot get through so quickly. > > > > But I have to make a preliminary decision within a couple of hours. > > > > The thing I need is a 32 bit counter (28 actually, but 32 lloks better :) > > which is up/down counter and which counts as: > > input is two (50% duty cycly) sequences. > > One sequence shifted against other by pi/2. Depending on a sign of shift > > the > > > counter should cont either up or down. > > > > Then I have to transmitt a counter value to cpu via 8 bit bus. > > However, the counter should continue work during lathing and > > transmission. > > > > Also, I need an output wich shows up or down counting, input for latch > > select, > > latch address and counter clear. > > > > Which fpga will you recommend for this and which one will work? > > > > Thanks, > > ~d > > > > On Thursday 21 November 2002 12:56, Stefan Wimmer wrote: > > > From: Dmitry [mailto:[email protected]] > > > > > > > has anybody experience in > > > > 1. cascading 74f579 (8 bit bidirectional counter or are there > > > > more bits > > > > up/down counters which work up to 10 MHz?) > > > > 2. interfacing it (5v vcc) with msp430 via latch > > > > > > Do you know about the Coolrunner CPLDs from Xilinx (developed by > > > Philips IIRC)? > > > http://www.xilinx.com/products/cr2/overview.htm > > > The software to configure the CPLDs (ISE WebPack) can be downloaded for > > > free. > > > http://www.xilinx.com/ise/ise_promo/ise5_cr2.htm > > > > > > They'd solve both 1. and 2. with the additional benefit that their > > > power consumption fit the MSP more than a 74Fxxx. > > > > > > HTH, > > > Stefan > > > > > > > > > ------------------------------------------------------- > > > This sf.net email is sponsored by:ThinkGeek > > > Welcome to geek heaven. > > > http://thinkgeek.com/sf > > > _______________________________________________ > > > Mspgcc-users mailing list > > > [email protected] > > > https://lists.sourceforge.net/lists/listinfo/mspgcc-users > > > > -- > > /******************************************************************** > > ("`-''-/").___..--''"`-._ (\ Dimmy the Wild UA1ACZ > > `6_ 6 ) `-. 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