Ryan Osial wrote: > > It's gone through a second iteration of coding for the controller and > glue. I put them through the Petter's testbench and I get the same > results, so as far as I can tell, it can operate as a drop in > replacement. Synthesis-wise, I have not yet been able to try it. My > laptop's 5GB harddrive doesn't cut it for ISPLever. The code should > work without many modifications, but that's just a guess. > It almost synthesizes :-). BTW, it's nice to see the full implementation.
/home/petter/src/ogp/spi_prom_alt-0.1/spi_prom_ctrl_alt.v:79:10:79:18: warning: No assignment to last_addr /home/petter/src/ogp/spi_prom_alt-0.1/spi_prom_ctrl_alt.v:92:0:92:5: warning: Pruning Register SCK_reg_3 /home/petter/src/ogp/spi_prom_alt-0.1/spi_prom_ctrl_alt.v:104:0:104:5: note: Trying to extract state machine for register state Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 /home/petter/src/ogp/spi_prom_alt-0.1/spi_prom_ctrl_alt.v:90:4:90:10: Only one always block may assign a given variable SCK_reg > Additionally, the prom simulator is more fleshed out. [Which helped > debug the controller] Everything but block protection is coded. I > haven't tested the segment and block erase thoroughly enough to call > it good, but it's in there and works for my small test case. Thanks for the updated simulator! > Something to note about the simulator. write protection is in there, > but I compile it out for Petter's testbench so the tb will get the > expected results. The simulator's more exotic commands like chip id > and status register write were tested out using my own testbench and > controller. > I attach a new test bench (and tweaked Makefile) which fixes the problem. This should work if copied along with Ryan's spi_prom_sim_alt.v into my previously posted spi_prom-0.2.tar.bz2.
module spi_test;
reg clock, _reset;
initial begin
$dumpfile("test.vcd");
$dumpvars;
#3;
_reset = 0;
#101;
_reset = 1;
#100000;
$finish;
end
initial begin
clock = 1;
forever begin
#10;
clock = !clock;
end
end
reg [31:0] write_data;
reg [3:0] byte_enables;
wire [31:0] read_data;
wire read_valid, busy;
reg do_read, do_write;
wire [23:0] addr;
wire SI, SCK;
wire SO, CE_;
spi_prom_sim_alt sps(
.SI(SI),
.SO(SO),
.CE_(CE_),
.SCK(SCK)
);
spi_controller sc (
.clock (clock),
.reset_ (_reset),
.busy (busy),
.addr (addr[23:2]),
.write_data (write_data),
.byte_enables (byte_enables),
.read_data (read_data),
.read_out_valid (read_valid),
.do_read (do_read),
.do_write (do_write),
.SI (SI),
.SO (SO),
.CE_ (CE_),
.SCK (SCK),
.read_cmd (8'h0b), // 8'h03 slow, 81h0b
.read_dummy_byte (1'b1),
.write_cmd (8'h02)
);
reg[23:0] read_addr;
reg[23:0] write_addr;
// hack to allow read in behavioral black
assign addr = read_addr | write_addr;
// read
// ----
reg cio_wanttoread;
reg[23:0] cio_read_addr;
initial cio_wanttoread = 0;
always @(posedge clock) begin
if (!busy) do_read <= 0;
if ((!do_read || !busy) && cio_wanttoread) begin
do_read <= 1;
read_addr <= cio_read_addr;
cio_wanttoread <= 0;
end
if (read_valid)
$display("test: read %x", read_data);
end
task cio_read;
input[23:0] addr_arg;
begin
cio_read_addr = addr_arg;
cio_wanttoread = 1;
#20;
while (cio_wanttoread) #20;
end endtask
// write
// -----
task cio_write; // do an 8 bit write
input[23:0] addr_arg;
input[3:0] byte_enables_arg;
input[32:0] write_data_arg;
begin
$display("test: write enable");
write_addr = 24'b0;
byte_enables = 4'b1111;
write_data = 32'h06000000; // write enable
do_write = 1;
#20;
do_write = 0;
#1000;
$display("test: write %x to %xen%b",
write_data_arg, addr_arg, byte_enables_arg);
write_addr = addr_arg;
byte_enables = byte_enables_arg;
write_data = write_data_arg;
do_write = 1;
#20;
write_addr = 24'b0;
do_write = 0;
#1000;
end endtask
/* For testing the controller */
reg[23:0] p;
reg[3:0] enables;
reg[31:0] x;
initial begin
$display("time addr 0EBV read E write I O E C");
$monitor("%4d %3x %1d%1d%1d%1d %4x %1d %4x %4b %d %d %d %d",
$time, addr, _reset, do_read, busy, read_valid, read_data,
do_write, write_data, byte_enables, SI, SO, CE_, SCK);
read_addr = 24'b0; // set to zero for write since it's ORed into addr
#23;
do_read = 0;
do_write = 0;
while (!_reset) #20;
// Write some bytes
cio_write(24'b0, 4'b1111, 32'h60000000); // chip erase
for (p = 8; p < 16; p = p + 4) begin
x = p == 8? 'hCAFEBABE : 'hdeadbeef;
for (enables = 4'b0001; enables; enables = enables << 1)
cio_write(p, enables, x);
end
// Read some 32 bit words
write_addr = 24'b0; // set to zero for read since it's ORed into addr
cio_read(8);
cio_read(8);
cio_read(12);
$display("Finisded last command.");
end
/* For testing the simulation model
reg [31:0] cmd, data;
integer i;
reg ce_;
reg si;
reg sck;
assign CE_ = ce_;
assign SI = si;
assign SCK = sck;
initial begin
$monitor("%4d %x %x", $time, cmd, data);
cmd = 'h0b000000;
ce_ = 1;
si = 0;
sck = 0;
while (!_reset) #20;
#20;
ce_ = 0;
for (i=0; i<32; i=i+1) begin
sck = 0;
si = 'bx;
#3;
si = cmd[31];
cmd = cmd << 1;
#7;
sck = 1;
#7;
si = 'bx;
#3;
end
si = 'bx;
for (i=0; i<39; i=i+1) begin
sck = 0;
#10;
sck = 1;
data = {SO, data[31:1]};
#10;
end
sck = 0;
#10;
data = {SO, data[31:1]};
ce_ = 1;
end
*/
endmodule
SYNTHC = ispsympc
#SYNTHC = iverilog -tfpga
default: spi_controller.edif
.PHONY: default
test:
iverilog spi_controller.v spi_prom_sim_alt.v spi_test.v spi_nosynth.v
&& ./a.out
%.edif: %.v
$(SYNTHC) -m $* $+ -o $@
%.xnf: %.v
iverilog -txnf -DTEST_SYNTH $< -o $@
spi_controller.edif: fakes.v
.PHONY: clean
clean:
rm -f a.out *.o *.vm *.vhm *.edif *.vcd
smime.p7s
Description: S/MIME Cryptographic Signature
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