On Saturday 10 June 2006 16:57, Timothy Miller wrote: > On 6/10/06, Hamish <[EMAIL PROTECTED]> wrote: > > What exactly doesn't it like about the code? Is it somply complaining > > because there's two (Almost) identical always blocks > > > > always @(posedge clock) SCK_reg <= #1 1; > > always @(negedge clock) SCK_reg <= #1 CE_; > > > > Which both assign to SCK_reg? In which case it doesn't seem to understand > > that (presumably) SCK_reg should be assigned 1 on the rising edge of the > > clock, and CE_ on the falling edge... > > > > Do I read it correctly? And what should be the way to specify an action > > on the rising or falling edge of the clock in verilog? > > > > [Sorry. Just wondering really if I'm reading this correctly]. > > There isn't one in Verilog. For synthesis, you cannot assign to the > same net or register from two different places, and there's no > construct for assigning on two edges. (Although, you can assign to A > on pos, B on neg, and then mux them together, but that's not what we > want.) I had given this as a simulation-only example, but Petter put > it in his code directly.
Just to elaborate on this for people who don't hold EE qualifications... :P Most registers in an FPGA are implemented as "master-slave" flip-flops, which have two "stages": an input stage, and an output stage. The input stage is enabled when the clock is low, and the output stage when the clock is high. This has the effect that between falling edge and rising edge, the input stage receives the new register value, and at the rising edge that value propagates to the output stage. So it is physically _impossible_ to make it latch on both rising edge and falling edge. :) It's easy to make them latch on falling edge by simply inverting the clock, or to add an enable signal that gates the clock, but you _can't_ make them latch twice a cycle. This design of register is used for the _vast_majority_ of registers on an FPGA, because (a) they're physically small, (b) they're very flexible, and (c) they're good enough for anything you're likely to want to do with an FPGA. DDR registers are complex and physically large, so they're typically placed only on the FPGA's IOs where there's often literally no alternative than to use them. Hope that's informative. Peter P.S. I have an exam on this _exact_ subject on Monday -- wish me luck please! -- Quake II build tools maintainer http://tinyurl.com/fkldd v2sw6YShw7$ln5pr6ck3ma8u6/8Lw3+2m0l7Ci6e4+8t4Eb8Aen5+6g6Pa2Xs5MSr5p4 hackerkey.com
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