Hamish wrote: > On Friday 09 June 2006 20:46, Petter Urkedal wrote: > >> /home/petter/src/ogp/spi_prom_alt-0.1/spi_prom_ctrl_alt.v:90:4:90:10: >> Only one always block may assign a given variable SCK_reg >> > Sorry. I don't read Verilog (Yet :). I've duplicated what you got here with > ISPLever, and am trying to find my way through it (Mainly so I can try out > the bits of ISPLever like block map etc so I can see what they look like). > > What exactly doesn't it like about the code? Is it somply complaining because > there's two (Almost) identical always blocks > > always @(posedge clock) SCK_reg <= #1 1; > always @(negedge clock) SCK_reg <= #1 CE_; > > Which both assign to SCK_reg? In which case it doesn't seem to understand > that > (presumably) SCK_reg should be assigned 1 on the rising edge of the clock, > and CE_ on the falling edge... > > Do I read it correctly? And what should be the way to specify an action on > the > rising or falling edge of the clock in verilog? >
Yes, it is correct. I didn't understand it myself until Tim explained it. The reason is that we are driving the PROM, and we want to carefully time all inputs to the SPI, including the clock. The SPI PROM samples on positive clock, and we want to make sure that is at the middle of the valid data we feed it. If we used the FPGA clock directly, then SI would lag slightly. Also, the use of CE_ is only to disable the clock when the PROM is unused. I should point out the Ryan's code contains a commented alternative that I should have switch too before trying to synthesize the code. So, the only error from the output is my fault. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
