On 6/10/06, Hamish <[EMAIL PROTECTED]> wrote:
What exactly doesn't it like about the code? Is it somply complaining because there's two (Almost) identical always blocks always @(posedge clock) SCK_reg <= #1 1; always @(negedge clock) SCK_reg <= #1 CE_; Which both assign to SCK_reg? In which case it doesn't seem to understand that (presumably) SCK_reg should be assigned 1 on the rising edge of the clock, and CE_ on the falling edge... Do I read it correctly? And what should be the way to specify an action on the rising or falling edge of the clock in verilog? [Sorry. Just wondering really if I'm reading this correctly].
There isn't one in Verilog. For synthesis, you cannot assign to the same net or register from two different places, and there's no construct for assigning on two edges. (Although, you can assign to A on pos, B on neg, and then mux them together, but that's not what we want.) I had given this as a simulation-only example, but Petter put it in his code directly. The solution is to use a DDR flipflop I/O buffer, and the correct one for Lattice is this: ODDRXC ddr_ff (.CLK(clock), .DA(for_rising), .DB(for_falling), .RST(reset), .Q(to_pin)); And then we add an I/O driver separately to connect to_pin to a type of I/O, but that's optional depending on the type. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
