On 6/12/06, Timothy Miller <[EMAIL PROTECTED]> wrote:
These proms require an explicit write-enable command before programming and a write-disable after.
Tim, I'd like to hop in here on write-enable while it's on topic. We might be talking about different write-enables since there's at least two 'write enables' that I know of: the write protect pin and the write enable latch inside the prom. If we're talking about the latch, that's not exactly how I've been reading the spec. I haven't written for a prom over spi specifically before so I want to be sure we're on the same page. From page 6 of the prom data sheet: http://www.sst.com/downloads/datasheet/S71242.pdf Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to "1", it indicates the device is Write enabled. If the bit is set to "0" (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: o Power-up o Write-Disable (WRDI) instruction completion o Byte-Program instruction completion o Auto Address Increment (AAI) programming reached its highest memory address o Sector-Erase instruction completion o Block-Erase instruction completion o Chip-Erase instruction completion I've interpreted the docs as saying all writes except AAI have an implicit write-disable after executing the command. However, I'd like to make sure I'm reading this right because otherwise I fear the little things may start to add up as we expand out to other modules. -Ryan _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
