Am 21.04.2015 um 09:19 schrieb Paul Fertser: > On Mon, Apr 20, 2015 at 02:24:41PM +0200, Andreas Färber wrote: >> Am 20.04.2015 um 13:49 schrieb Andreas Färber: >>> xmc4500-application-kit-sdram.cfg with http://openocd.zylin.com/#/c/2721/ : >>> >> [...] >>>> reset init >>> SWD IDCODE 0x2ba01477 >>> timed out while waiting for target halted >>> TARGET: xmc4500.cpu - Not halted >>> in procedure 'reset' >>> in procedure 'ocd_bouncer' >>> >>> >>> Halt timed out, wake up GDB. >>>> >> >> ../../bin/bin/openocd -f openocd.cfg -c init -c "reset init" -d3 2> >> sdram-reset-init.log > > This log looks like hardware SRST line on this target _fully_ resets > it (as if it was power-cycled) so the special reset vector catch bit > set before asserting SRST is lost and the target gets to run after > deasserting. This looks surprisingly similar to what Dominic reports > with LPC1857. > > Do you think you might find some official vendor recommendation on how > to implement "halt on reset" operation? Can you probably call their > support line of find that in the documentation please?
I see some bits on halt after reset in chapter 27.4.2 of the XMC4500 Reference Manual v1.5, available from http://www.infineon.com/cms/en/product/microcontrollers/32-bit-xmc4000-industrial-microcontrollers-arm%EF%BF%BDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFD-cortex!22-m4/channel.html?channel=db3a30433580b3710135a03abaf9385e&tab=2#db3a304412b407950112b4095ddb01f4 What I read out of this is that while some start-up software executes but before the user software executes, two CoreSight registers need to be written (CTRL/STAT.CDBGPWRUPREQ, DHCSR.C_DEBUGEN) and a breakpoint be placed on the first user instruction, for halt on power-up to work. Unless a reset of the debug domain is specifically requested, those settings will then remain in place for subsequent warm resets. Section "SWJ-DP reset" mentions nTRST initializing the TAP controller. Section "SW-DP reset" mentions PORESETn. In chapter 27.3.1.1 that is. And the boards require the use of SWD unless modifications are made - Jeff mentioned some resistor a while back. Anyway, the halt-on-reset logic doesn't seem too specific to XMC4500, with the Infineon manual pointing to the "ARMv7-M Architecture Reference Manual". Regards, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Jennifer Guild, Dilip Upmanyu, Graham Norton; HRB 21284 (AG Nürnberg) ------------------------------------------------------------------------------ BPM Camp - Free Virtual Workshop May 6th at 10am PDT/1PM EDT Develop your own process in accordance with the BPMN 2 standard Learn Process modeling best practices with Bonita BPM through live exercises http://www.bonitasoft.com/be-part-of-it/events/bpm-camp-virtual- event?utm_ source=Sourceforge_BPM_Camp_5_6_15&utm_medium=email&utm_campaign=VA_SF _______________________________________________ OpenOCD-devel mailing list OpenOCD-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openocd-devel
