Duane,
> Can we get confirmation about how the JRC works in OMAP?
>
> Is the following assertion true?
>
> When a TAP is enabled, it is always enabled at a FIXED
> position within the chain?
>
i've done some tests comparing the davinci dm-355 board(it has basically the
same ICEPick as the OMAP35xx) with the openocd config and bdi2000 configs. it
does appear that the taps are in a fixed position.
> To describe it another way - Assume there are 3 taps.
>
> (1) ICE Pick - the JRC
> (2) An ARM CPU Tap
> (3) A DSP CPU Tap
>
> The ARM CPU - if it is enabled is ALWAYS after the JRC and
> ALWAYS before the DSP (if it is enabled).
>
> The JRC can *NEVER* swap the order of any two taps.
>
for the davinci, the order is:
1) ARM
2) ETB
3) ICEPick
when EMU0/EMU1 are pulled low, the ICEPick TAP is on and is forced to default
with the two TAPS enabled. when EMU0/EMU1 are pulled high, the ICEPick has to
be programmed in the same manner as the OMAP35xx's ICEPick.
> It sure seems like this is true.
>
> Today - OpenOCD - and most other JTAG programs assume the
> following:
>
> 1) The tap is IN BYPASS (and has length 1)
> or
> 2) The tap is *NOT* in BYPASS (and has length N)
>
> It seems, all we must do is introduce a 3rd state.
>
> 3) The tap is Disabled and has Length 0.
>
this sounds completely reasonable. if you compare the bdi config files for the
davinci and the omap35xx there are some differences:
davinci
; Configure ICEPick module to make ARM926 TAP visible
SCANINIT r0:w10000:
SCANINIT r1:t1:w1000:t0:w1000: ;assert reset and toggle TRST
SCANINIT i6=07:d8=89:i6=02: ;connect and select router
SCANINIT d32=81000082: ;set IP control
SCANINIT d32=a018206f: ;configure TAP0
SCANINIT d32=a018216f:cl5: ;enable TAP0, clock 5 times in RTI
SCANINIT i10=ffff ;scan bypass
omap35xx
; Configure ICEPick module to make Cortex-A8 DAP-TAP visible
SCANINIT t1:w1000:t0:w1000: ;toggle TRST,
SCANINIT ch10:w1000: ;clock TCK with TMS high and wait
SCANINIT i6=07:d8=89:i6=02: ;connect and select router
SCANINIT d32=81000080: ;IP control: KeepPowered
SCANINIT d32=a3002048: ;TAP3: DebugConnect, ForcePower, ForceActive
SCANINIT d32=81000081: ;IP control: KeepPowered, SysReset
SCANINIT d32=a3002148: ;enable TAP3
SCANINIT cl10:i10=ffff ;clock 10 times in RTI, scan bypass
notice the arm core on the davinci is at TAP0 and the arm core on the omap is
at TAP3. based on the documents that have been posted for the OMAP35xx combined
with the information from the BDI config, the OMAP35xx tap looks like this:
1) DSP
2) ETB
3) ARM
4) ICEPick
any changes/development we do to support JRC's can be tested currently with the
DM-355 and related davinci boards, as they already have debug support in the
main tree of openocd. this gives you a reference for testing.
Dave Anders
TinCanTools
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