On Fri, Jan 29, 2010 at 10:50 AM, Edgar Grimberg <edgar.grimb...@zylin.com> wrote: > On Tue, Jan 26, 2010 at 5:38 AM, David Brownell <davi...@pacbell.net> wrote: >> On Tuesday 19 January 2010, Øyvind Harboe wrote: >>> Run the following and it will fail to halt occasionally. This is not a >>> regression, >>> but I thought I'd post this tip on how to reproduce flaky reset problems... >> >> Got any more info on this? Just curious. >
Another type of reset issue: > reset init 10 kHz JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3) srst pulls trst - can not reset into halted mode. Issuing halt after reset. Jazelle debug entry -- BROKEN! Jazelle state handling is BROKEN! target state: halted target halted in Jazelle state due to debug-request, current mode: Supervisor cpsr: 0x010000d3 pc: 0x00000012 500 kHz NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'. NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'. This is not as severe, since I can resume the normal workflow even with this scary messages. Log level 3 is also on it's way... -- Edgar Grimberg System Developer Zylin AS ZY1000 JTAG Debugger http://www.zylin.com/zy1000.html Phone: (+47) 51 63 25 00 _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
