On Friday 29 January 2010, Edgar Grimberg wrote: > JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: > 0xf0f0, ver: 0x3) > srst pulls trst - can not reset into halted mode. Issuing halt after reset. > Jazelle debug entry -- BROKEN! > Jazelle state handling is BROKEN! > target state: halted > target halted in Jazelle state due to debug-request, current mode: Supervisor > cpsr: 0x010000d3 pc: 0x00000012
And yet ARM7TDMI's CPSR doesn't support the J bit. :) That 0x01000000 bit is trouble. I wonder how it got set. It seems to be "reserved", so maybe in this case that should be transalted as "ignore" (we'd need to mask it out) rather than "should be zero". - Dave _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
