Good point...  also you could change the width of the keepout lines to get your 
clearance around the edge of the board...  more than one way to skin a cat 
depending on where you want to end up...

duane

> -----Original Message-----
> From: [EMAIL PROTECTED]
> [mailto:[EMAIL PROTECTED] Behalf Of M P
> Sent: Friday, April 21, 2006 4:46 AM
> To: [email protected]
> Subject: Re: [PEDA] Fwd: 99SE PCB Component gone afar.
> 
> 
> Duane,
> 
> if you setup a clearance rule between keepout object kind and 
> whole board, 
> you could have outlines on keepout layer identical to real 
> board outlines 
> (probably found on some other layer).
> 
> Igor
> 
> >From: "Duane Foster" <[EMAIL PROTECTED]>
> >Reply-To: Protel EDA Discussion List <[email protected]>
> >To: "Protel EDA Discussion List" <[email protected]>
> >Subject: Re: [PEDA] Fwd:  99SE PCB Component gone afar.
> >Date: Thu, 20 Apr 2006 13:59:04 -0700
> >
> >If I use the autorouter, then I usually draw the keepout 
> inside of the 
> >actual board outline.  So I have usually used the drill 
> drawing layer for 
> >the board outline.  This is 99SE and earlier of course.
> >
> >duane
> >
> > > -----Original Message-----
> > > From: [EMAIL PROTECTED]
> > > [mailto:[EMAIL PROTECTED] Behalf Of 
> [EMAIL PROTECTED]
> > > Sent: Thursday, April 20, 2006 1:53 PM
> > > To: [email protected]
> > > Subject: Re: [PEDA] Fwd: 99SE PCB Component gone afar.
> > >
> > >
> > > All/anyone...
> > >
> > > Just for curiosity's sake, isn't the keepout layer the
> > > proscribed layer
> > > for defining board outlines? It's been quite a while (20
> > > years) but as I
> > > recall, Protel manuals specified use of the keepout layer for
> > > just that
> > > purpose in their tutorials.
> > >
> > > aj
> > > >-----Original Message-----
> > > >From: [EMAIL PROTECTED]
> > > >[mailto:[EMAIL PROTECTED] On Behalf Of Jon Elson
> > > >Sent: Thursday, April 20, 2006 4:09 PM
> > > >To: Protel EDA Discussion List
> > > >Subject: Re: [PEDA] Fwd: 99SE PCB Component gone afar.
> > > >
> > > >
> > > >
> > > >David Cary wrote:
> > > >
> > > >>Dear Brad Velander,
> > > >>
> > > >>Thank you. This is something I will add to the FAQ.
> > > 
> >>http://massmind.org/techref/app/pwb_design_flow.htm#placement_FAQ
> > > >>
> > > >>--
> > > >>David Cary
> > > >>
> > > >>On 4/13/06, Brad Velander <[EMAIL PROTECTED]> wrote:
> > > >>
> > > >>
> > > >>>... Used to be that when I updated a PCB and it brought in
> > > >the new components, they were typically in the very top right
> > > >quadrant of the working space (to hell and gone).
> > > >>>
> > > >>>
> > > >>...
> > > >>
> > > >>
> > > >>>I don't know what has changed but more recently I get the
> > > >components coming in just to the right and upwards from my
> > > >board outline.
> > > >>>
> > > >>>
> > > >>...
> > > >>
> > > >>
> > > >>>        Actually I just thought of what it could have been
> > > >that changed for me. Do you use the keepout layer for your
> > > >board outlines? Here at my new employer that is something I am
> > > >now doing different than previously, we use the Keepout layer
> > > >for our board outline. I will have to test that, previously I
> > > >used Mech Layer 1 for my board outlines and typically had
> > > >nothing on the keepout layer.
> > > >>>
> > > >>>
> > > >Yes, if the keepout border exists, the parts hug to the right
> > > >of it.  If no keepout primitives are found, then the parts go
> > > >to the upper right edge of the workspace, kind of out in 
> neverland.
> > > >
> > > >Jon
> > > >
> > > >
> > > >
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