On Wednesday 20 July 2005 20:02, Alex Phillips wrote: > > For the purposes of Prime testing, dual-core processors behave exactly like > an SMP mobo with 2 CPUs fitted, however you only get half as much memory > bus bandwidth for each CPU, compared with a proper SMP mobo,
Actually this is a memory controller issue. There are lots of "hobbyist" dual-cpu mobos which aren't "proper" i.e. have only one memory controller and are therefore subject to the sort of blocking you describe. > so for > "real-world" compute-intensive applications performance can take a > substantial hammering. I've seen figures of over 50% idle on the second > core of a dual-core processor. Run trial factoring on one CPU in parallel with LL testing on the other, you will get very close to 100% utilization of both cores - however LL testing is never fully efficient (except when the work vectors fit into L1 cache) as there is always some wastage of CPU cycles whilst dirty cache lines are written to memory so that new cache lines can be made available. Even on simple uniprocessor setups. The point is that trial factoring has a _very_ small demand for memory bandwidth. Regards Brian Beesley _______________________________________________ Prime mailing list [email protected] http://hogranch.com/mailman/listinfo/prime
