Yes, AMD building the memory controller into the CPU itself involves a performance compromise. You can still have an N-opteron mobo using multiported memory but non-cached memory accesses between "remote" CPUs will then probably be _faster_ than non-cached memory accesses between CPUs on the same chip. The complication is that cached memory may be shared between CPUs on the same chip. Can't have everything without having one socket per CPU, I guess.
the opteron 800 has 3 hypertransport channels per CPU which allows a fully meshed system where all memory is no more than one hyperchannel away. the latency difference between local memory and remote memory is minimal in 4 CPU systems.
No, systems with lots of Xeons (certainly more than 4) pretty well have to use multiple memory controllers accessing multiported memory if they're not going to be completely crippled.
very few people are building Xeon systems with more than 4 CPUs. All the large scale systems Xeon I'm familiar with are clusters of 2 or 4 CPU systems using gigibit networking or Eclipse for the cluster interconnect. each cluster node runs its own OS image.
HP has their F8 chipset that supports 8 Xeon MP (used in the Proliant DL740/760, but I believe it still only has a single memory bus as they have a RAM hotswap "RAID" scheme where 5 DIMMs are striped like RAID-4 and provide one cache line (4 dimms wide) at a time.
_______________________________________________ Prime mailing list [email protected] http://hogranch.com/mailman/listinfo/prime
