On Sat, 28 Sept 2024 at 12:34, Peter Maydell <peter.mayd...@linaro.org> wrote: > > On Tue, 24 Sept 2024 at 23:18, Alistair Francis <alistai...@gmail.com> wrote: > > > > The following changes since commit 01dc65a3bc262ab1bec8fe89775e9bbfa627becb: > > > > Merge tag 'pull-target-arm-20240919' of > > https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-09-19 > > 14:15:15 +0100) > > > > are available in the Git repository at: > > > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240925-1 > > > > for you to fetch changes up to 6bfa92c5757fe7a9580e1f6e065076777cae650f: > > > > bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files > > (2024-09-24 12:53:16 +1000) > > > > ---------------------------------------------------------------- > > RISC-V PR for 9.2 > > > > * Add a property to set vl to ceil(AVL/2) > > * Enable numamem testing for RISC-V > > * Consider MISA bit choice in implied rule > > * Fix the za64rs priv spec requirements > > * Enable Bit Manip for OpenTitan Ibex CPU > > * Fix the group bit setting of AIA with KVM > > * Stop timer with infinite timecmp > > * Add 'fcsr' register to QEMU log as a part of F extension > > * Fix riscv64 build on musl libc > > * Add preliminary textra trigger CSR functions > > * RISC-V IOMMU support > > * RISC-V bsd-user support > > * Respect firmware ELF entry point > > * Add Svvptc extension support > > * Fix masking of rv32 physical address > > * Fix linking problem with semihosting disabled > > * Fix IMSIC interrupt state updates > > > > This fails the riscv qos-tests on s390x. My guess is that the new > IOMMU support has endianness bugs and fails on bigendian hosts.
I have also noticed that the license text comments in the iommu patches are confused. That must be fixed before we can accept them. (see my reply to patch 16.) thanks -- PMM
