Hi Cedric,
> From: Cédric Le Goater <c...@kaod.org>
> Sent: Thursday, February 6, 2025 3:23 PM
> To: Jamin Lin <jamin_...@aspeedtech.com>; Andrew Jeffery
> <and...@codeconstruct.com.au>; Peter Maydell <peter.mayd...@linaro.org>;
> Steven Lee <steven_...@aspeedtech.com>; Troy Lee <leet...@gmail.com>;
> Joel Stanley <j...@jms.id.au>; open list:ASPEED BMCs
> <qemu-...@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_...@aspeedtech.com>; Yunlin Tang
> <yunlin.t...@aspeedtech.com>
> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of
> INTC controllers for AST2700 A1
>
> > The design of the OR gates for GICINT 196 is as follows:
> > It has interrupt sources ranging from 0 to 31, with its output pin
> > connected to INTC_IO "T0 GICINT_196".
> > The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4,
> > and its bit 4 output should be connected to GIC 196.
> > The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as
> following:
> > Bit 0 -> GIC 192
> > Bit 1 -> GIC 193
> > Bit 2 -> GIC 194
> > Bit 3 -> GIC 195
> > Bit 4 -> GIC 196
> >
> > Jamin
> >
> |-----------------------------------------------------------------------------------------------------
> --|
> > |
> AST2700 A1 Design |
> > | To GICINT196
> |
> > |
> |
> > | ETH1 |-----------|
> |--------------------------| |--------------| |
> > | -------->|0 | |
> INTC_IO | | orgates[0] | |
> > | ETH2 | 4|
> orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | |
> > | -------->|1 5|
> orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | |
> > | ETH3 | 6|
> orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | |
> > | -------->|2 19|
> orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| |
> > | UART0 |
> 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 |
> | |
> > | -------->|7 21|
> orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | |
> > | UART1 | 22|
> orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | |
> > | -------->|8 23|
> orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | |
> > | UART2 | 24|
> orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | |
> > | -------->|9 25|
> orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | |
> > | UART3 | 26|
> |--------------------------| |--------------| | |
> > | ---------|10 27|
> | |
> > | UART5 | 28|
> | |
> > | -------->|11 29|
> | |
> > | UART6 | |
> | |
> > | -------->|12 30|
> |-----------------------------------------------------------------------| |
> > | UART7 | 31| |
> |
> > | -------->|13 | |
> |
> > | UART8 | OR[0:31] | |
> |------------------------------| |----------| |
> > | -------->|14 | | |
> INTC | | GIC | |
> > | UART9 | | |
> |inpin[0:0]--------->outpin[0] |---------->|192 | |
> > | -------->|15 | |
> |inpin[0:1]--------->outpin[1] |---------->|193 | |
> > | UART10 | | |
> |inpin[0:2]--------->outpin[2] |---------->|194 | |
> > | -------->|16 | |
> |inpin[0:3]--------->outpin[3] |---------->|195 | |
> > | UART11 | | |-------------->
> |inpin[0:4]--------->outpin[4] |---------->|196 | |
> > | -------->|17 |
> |inpin[0:5]--------->outpin[5] |---------->|197 | |
> > | UART12 | |
> |inpin[0:6]--------->outpin[6] |---------->|198 | |
> > | -------->|18 |
> |inpin[0:7]--------->outpin[7] |---------->|199 | |
> > | |-----------|
> |inpin[0:8]--------->outpin[8] |---------->|200 | |
> > |
> |inpin[0:9]--------->outpin[9] |---------->|201 | |
> >
> |-----------------------------------------------------------------------------------------------------
> --|
> >
> |-----------------------------------------------------------------------------------------------------
> --|
> > | ETH1 |-----------|
> orgates[1]------->|inpin[1]|---------->outpin[10]|---------->|128 | |
> > | -------->|0 |
> orgates[2]------->|inpin[2]|---------->outpin[11]|---------->|129 | |
> > | ETH2 | 4|
> orgates[3]------->|inpin[3]|---------->outpin[12]|---------->|130 | |
> > | -------->|1 5|
> orgates[4]------->|inpin[4]|---------->outpin[13]|---------->|131 | |
> > | ETH3 |
> 6|---->orgates[5]------->|inpin[5]|---------->outpin[14]|---------->|132
> |
> |
> > | -------->|2 19|
> orgates[6]------->|inpin[6]|---------->outpin[15]|---------->|133 | |
> > | UART0 | 20|
> orgates[7]------->|inpin[7]|---------->outpin[16]|---------->|134 | |
> > | -------->|7 21|
> orgates[8]------->|inpin[8]|---------->outpin[17]|---------->|135 | |
> > | UART1 | 22|
> orgates[9]------->|inpin[9]|---------->outpin[18]|---------->|136 | |
> > | -------->|8 23|
> |------------------------------| |----------| |
> > | UART2 | 24|
> |
> > | -------->|9 25| AST2700 A0
> Design |
> > | UART3 | 26|
> |
> > | -------->|10 27|
> |
> > | UART5 | 28|
> |
> > | -------->|11 29| GICINT132
> |
> > | UART6 | |
> |
> > | -------->|12 30|
> |
> > | UART7 | 31|
> |
> > | -------->|13 |
> |
> > | UART8 | OR[0:31] |
> |
> > | -------->|14 |
> |
> > | UART9 | |
> |
> > | -------->|15 |
> |
> > | UART10 | |
> |
> > | -------->|16 |
> |
> > | UART11 | |
> |
> > | -------->|17 |
> |
> > | UART12 | |
> |
> > | -------->|18 |
> |
> > | |-----------|
> |
> > |
> |
> >
> > |---------------------------------------------------------------------
> > ----------------------------------|
>
>
> Nice ! When you send the intc series for ast2700a1 support, could you please
> include this diagram in file docs/specs/aspeed-intc.rst with some description
> ?
> The text could be the same as the cover letter.
>
Will add
Thanks for suggestion
Jamin
>
> Thanks,
>
> C.
