The GICv5 PPI pending status is handled by two registers, one of which is write-1-to-set and one of which is write-1-to-clear. The pending state is read-only for PPIs where the handling mode is Edge.
Signed-off-by: Peter Maydell <[email protected]> --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 44 ++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4574f7005d..980abda3ca 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -606,6 +606,7 @@ typedef struct CPUArchState { /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */ uint64_t ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; + uint64_t ppi_pend[GICV5_NUM_PPIS / 64]; } gicv5_cpuif; struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 6fbc962131..4647fd40ba 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -199,6 +199,26 @@ static void gic_ppi_sactive_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, old | value); } +static void gic_ppi_cpend_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t old = raw_read(env, ri); + /* If ICC_PPI_HMR_EL1[n].HM is 1, PEND bits are RO */ + uint64_t hm = env->gicv5_cpuif.ppi_hm[ri->opc2 & 1]; + value &= ~hm; + raw_write(env, ri, old & ~value); +} + +static void gic_ppi_spend_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t old = raw_read(env, ri); + /* If ICC_PPI_HMR_EL1[n].HM is 1, PEND bits are RO */ + uint64_t hm = env->gicv5_cpuif.ppi_hm[ri->opc2 & 1]; + value &= ~hm; + raw_write(env, ri, old | value); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { /* * Barrier: wait until the effects of a cpuif system register @@ -314,6 +334,30 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), .resetvalue = PPI_HMR1_RESET, }, + { .name = "ICC_PPI_CPENDR0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 4, + .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), + .writefn = gic_ppi_cpend_write, + }, + { .name = "ICC_PPI_CPENDR1_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 5, + .access = PL1_RW, .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), + .writefn = gic_ppi_cpend_write, + }, + { .name = "ICC_PPI_SPENDR0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 6, + .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), + .writefn = gic_ppi_spend_write, + }, + { .name = "ICC_PPI_SPENDR0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 13, .opc2 = 7, + .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), + .writefn = gic_ppi_spend_write, + }, }; void define_gicv5_cpuif_regs(ARMCPU *cpu) -- 2.43.0
