Implement the GICv5 registers which hold the priority of the PPIs. Each 64-bit register has the priority fields for 8 PPIs, so there are 16 registers in total. This would be a lot of duplication if we wrote it out statically in the array, so instead create each register via a loop in define_gicv5_cpuif_regs().
Signed-off-by: Peter Maydell <[email protected]> --- target/arm/cpu.h | 2 ++ target/arm/tcg/gicv5-cpuif.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 915a225f8e..b97f659352 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -608,6 +608,8 @@ typedef struct CPUArchState { uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; uint64_t ppi_pend[GICV5_NUM_PPIS / 64]; uint64_t ppi_enable[GICV5_NUM_PPIS / 64]; + /* The PRIO regs have 1 byte per PPI, so 8 PPIs to a register */ + uint64_t ppi_priority[GICV5_NUM_PPIS / 8]; } gicv5_cpuif; struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index c54e784dc4..60b495dd8f 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -225,6 +225,12 @@ static void gic_ppi_enable_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value); } +static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] = { /* * Barrier: wait until the effects of a cpuif system register @@ -382,5 +388,22 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu) { if (cpu_isar_feature(aa64_gcie, cpu)) { define_arm_cp_regs(cpu, gicv5_cpuif_reginfo); + + /* + * There are 16 ICC_PPI_PRIORITYR<n>_EL1 regs, so define them + * programmatically rather than listing them all statically. + */ + for (int i = 0; i < 16; i++) { + g_autofree char *name = g_strdup_printf("ICC_PPI_PRIORITYR%d_EL1", i); + ARMCPRegInfo ppi_prio = { + .name = name, .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, + .crm = 14 + (i >> 3), .opc2 = i & 7, + .access = PL1_RW, .type = ARM_CP_IO, + .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_priority[i]), + .writefn = gic_ppi_priority_write, .raw_writefn = raw_write, + }; + define_one_arm_cp_reg(cpu, &ppi_prio); + } } } -- 2.43.0
