The GICv5 devicetree binding specifies the "interrupts" property differently to GICv2 and GICv3 for PPIs: the first field is the architectural INTID.TYPE, and the second is the architectural INTID.ID. (The third field defining the level/edge trigger mode has the same values for GICv5 as it did for the older GICs.)
In the places in the virt board where we wire up PPIs (the timer and the PMU), handle the GICv5: * use the architectural constant GICV5_PPI for the type * use the architected GICv5 PPI numbers for the interrupt sources (which differ from the old ones and don't need to be adjusted via INTID_TO_PPI()) * leave the irqflags as-is Add some commentary in our include/hw/arm/fdt.h file about what the the constants defined there are valid for. Signed-off-by: Peter Maydell <[email protected]> --- hw/arm/virt.c | 23 +++++++++++++++++++---- include/hw/arm/fdt.h | 10 ++++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 6775062c5d..05c92e8482 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -421,7 +421,15 @@ static void fdt_add_timer_nodes(const VirtMachineState *vms) "arm,armv7-timer"); } qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); - if (vms->ns_el2_virt_timer_irq) { + if (vms->gic_version == VIRT_GIC_VERSION_5) { + /* The GICv5 architects the PPI numbers differently */ + qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", + GICV5_PPI, GICV5_PPI_CNTPS, irqflags, + GICV5_PPI, GICV5_PPI_CNTP, irqflags, + GICV5_PPI, GICV5_PPI_CNTV, irqflags, + GICV5_PPI, GICV5_PPI_CNTHP, irqflags, + GICV5_PPI, GICV5_PPI_CNTHV, irqflags); + } else if (vms->ns_el2_virt_timer_irq) { qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", GIC_FDT_IRQ_TYPE_PPI, INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, @@ -700,11 +708,18 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) qemu_fdt_add_subnode(ms->fdt, "/pmu"); if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { const char compat[] = "arm,armv8-pmuv3"; + qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", compat, sizeof(compat)); - qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", - GIC_FDT_IRQ_TYPE_PPI, - INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); + if (vms->gic_version == VIRT_GIC_VERSION_5) { + qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", + GICV5_PPI, GICV5_PPI_PMUIRQ, irqflags); + } else { + qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(VIRTUAL_PMU_IRQ), + irqflags); + } } } diff --git a/include/hw/arm/fdt.h b/include/hw/arm/fdt.h index c3d5015013..da5c9d4a8f 100644 --- a/include/hw/arm/fdt.h +++ b/include/hw/arm/fdt.h @@ -20,9 +20,19 @@ #ifndef QEMU_ARM_FDT_H #define QEMU_ARM_FDT_H +/* + * These are for GICv2/v3/v4 only; GICv5 encodes the interrupt type in + * the DTB "interrupts" properties differently, using constants that match + * the architectural INTID.Type. In QEMU those are available as the + * GICV5_PPI and GICV5_SPI enum values in arm_gicv5_types.h. + */ #define GIC_FDT_IRQ_TYPE_SPI 0 #define GIC_FDT_IRQ_TYPE_PPI 1 +/* + * The trigger type/level field in the DTB "interrupts" property + * has the same encoding for GICv2/v3/v4 and v5. + */ #define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1 #define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2 #define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4 -- 2.43.0
