On Fri, May 15, 2026 at 5:12 PM Philippe Mathieu-Daudé <[email protected]> wrote: > > In order to make the following commit easier to review, > factor aarch64_aa32_a57_init() out of aarch64_a57_initfn() > as a preliminary step. We only add a %aa32_only argument > to restrict AArch64 features. > > Suggested-by: Richard Henderson <[email protected]> > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > ---
Reviewed-by: Manos Pitsidianakis <[email protected]> > target/arm/cpu64.c | 36 ++++++++++++++++++++++++------------ > 1 file changed, 24 insertions(+), 12 deletions(-) > > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 7b2f09cf8ec..7dce17fdb20 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -686,17 +686,20 @@ void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error > **errp) > SET_IDREG(&cpu->isar, ID_AA64MMFR0, t); > } > > -static void aarch64_a57_initfn(Object *obj) > +static void aarch64_aa32_a57_init(Object *obj, bool aa32_only) > { > ARMCPU *cpu = ARM_CPU(obj); > ARMISARegisters *isar = &cpu->isar; > + const bool aarch64_enabled = !aa32_only; > > cpu->dtb_compatible = "arm,cortex-a57"; > set_feature(&cpu->env, ARM_FEATURE_V8); > set_feature(&cpu->env, ARM_FEATURE_NEON); > set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); > set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); > - set_feature(&cpu->env, ARM_FEATURE_AARCH64); > + if (aarch64_enabled) { > + set_feature(&cpu->env, ARM_FEATURE_AARCH64); > + } > set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); > set_feature(&cpu->env, ARM_FEATURE_EL2); > set_feature(&cpu->env, ARM_FEATURE_EL3); > @@ -727,10 +730,12 @@ static void aarch64_a57_initfn(Object *obj) > SET_IDREG(isar, ID_ISAR4, 0x00011142); > SET_IDREG(isar, ID_ISAR5, 0x00011121); > SET_IDREG(isar, ID_ISAR6, 0); > - SET_IDREG(isar, ID_AA64PFR0, 0x00002222); > - SET_IDREG(isar, ID_AA64DFR0, 0x10305106); > - SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); > - SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); > + if (aarch64_enabled) { > + SET_IDREG(isar, ID_AA64PFR0, 0x00002222); > + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); > + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); > + SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); > + } > cpu->isar.dbgdidr = 0x3516d000; > cpu->isar.dbgdevid = 0x01110f13; > cpu->isar.dbgdevid1 = 0x2; > @@ -742,14 +747,21 @@ static void aarch64_a57_initfn(Object *obj) > cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); > /* 2048KB L2 cache */ > cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7); > - set_dczid_bs(cpu, 4); /* 64 bytes */ > - cpu->gic_num_lrs = 4; > - cpu->gic_vpribits = 5; > - cpu->gic_vprebits = 5; > - cpu->gic_pribits = 5; > + if (aarch64_enabled) { > + set_dczid_bs(cpu, 4); /* 64 bytes */ > + cpu->gic_num_lrs = 4; > + cpu->gic_vpribits = 5; > + cpu->gic_vprebits = 5; > + cpu->gic_pribits = 5; > + } > define_cortex_a72_a57_a53_cp_reginfo(cpu); > } > > +static void aarch64_a57_initfn(Object *obj) > +{ > + aarch64_aa32_a57_init(obj, false); > +} > + > static void aarch64_a53_initfn(Object *obj) > { > ARMCPU *cpu = ARM_CPU(obj); > @@ -886,7 +898,7 @@ static void aarch64_max_initfn(Object *obj) > } > > if (tcg_enabled() || qtest_enabled()) { > - aarch64_a57_initfn(obj); > + aarch64_aa32_a57_init(obj, false); > } > > /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ > -- > 2.53.0 >
