On 15/5/26 20:04, Anton Johansson wrote:
According to version 20250508 of the unprivileged specification:
- vtype: bits 0..7 used, bit XLEN-1 illegal, rest reserved
=> fix to 64-bits.
- vxsat: bit 0 used, vxrm which would occupy bits 1..2 is stored
separately, and bits 3..31 are set to 0
=> fix to 8-bits.
- vxrm: 2 lowest bits are used for rounding mode, rest set to 0
=> fix to 8-bits.
- vstart: maximum value of VLMAX-1, where VLMAX is at most 2^16
=> fix to 32-bits as vstart is mapped to a TCG global.
- vl: maximum value of VLEN which is at most 2^16
=> fix to 32-bits as vl is mapped to a TCG global.
Fields are shuffled for reduced padding.
Note, the cpu/vector VMSTATE version is bumped, breaking migration from
older versions.
Signed-off-by: Anton Johansson <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
---
target/riscv/cpu.h | 12 +--
target/riscv/machine.c | 14 +--
target/riscv/translate.c | 12 ++-
target/riscv/vector_helper.c | 125 ++++++++++++++----------
target/riscv/insn_trans/trans_rvv.c.inc | 22 ++---
5 files changed, 103 insertions(+), 82 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
