On 18/05/26, Alistair Francis wrote: > On Sat, May 16, 2026 at 4:02 AM Anton Johansson via qemu development > <[email protected]> wrote: > > > > Hi, > > > > this is a first patchset moving towards single-binary support for riscv. > > Additional patchsets for hw/ and target/ are based on this one so it's > > best to make sure the approach taken is ok. Most patches in this set > > concern fields in CPUArchState which are either widened (usually to > > uint64_t) or fixed to a smaller size which handles all use cases. > > > > General purpose registers and fields mapped to TCG are dealt with by > > widening the type and applying an offset to tcg_global_mem_new() to > > correctly handle 32-bit targets on big endian hosts. > > > > Quick question to correct my understanding. AFAICT riscv64-softmmu is a > > superset of riscv32-softmmu which handles 32-, 64, and 128-bit ISAs, so > > concerning single-binary do we for the time being only need to support > > riscv64-softmmu? > > That's mostly right. > > In an ideal world there would be no riscv32-softmmu, just a > riscv64-softmmu which could handle all bit lengths. > > There are currently corner cases where riscv64-softmmu doesn't work as > well for 32-bit bit (I heard GDB debugging a 32-bit guest either > doesn't work or has problems). > > But focusing on riscv64-softmmu with the goal of dropping > riscv32-softmmu in the future is fine with me > > Alistair
Thanks for the clarification! Do you know if there's any performance regression to running 32-bit code under riscv64-softmmu? I assume there's more extensions/truncations? -- Anton Johansson rev.ng Labs Srl.
