SAA atomically adds rt to the naturally aligned 32-bit word at base and discards the old memory value.
Implement the common SAA/SAAD translator with TCG atomic_fetch_add_i64. The MemOp selects the word or doubleword transaction size. QEMU only has one Octeon CPU model today, so keep SAA/SAAD under the existing Octeon instruction feature bucket instead of adding a finer-grained Octeon+ feature bit. Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: James Hilliard <[email protected]> --- Changes v6 -> v7: - Use MO_32 for the word-size atomic transaction; the signedness bits are irrelevant for a discarded fetch-add result. (suggested by Philippe Mathieu-Daudé) Changes v2 -> v3: - Split SAA out of the combined Octeon arithmetic and memory instruction patch. (requested by Richard Henderson) Changes v3 -> v4: - Gate SAA/SAAD behind an Octeon+ feature bit. (reported by Richard Henderson) - Use the i64 TCG atomic add path for both word and doubleword sizes. (suggested by Richard Henderson) Changes v4 -> v5: - Drop the separate Octeon+ feature bit; QEMU only has one Octeon CPU model today. (comment by Richard Henderson) --- target/mips/tcg/octeon.decode | 4 ++++ target/mips/tcg/octeon_translate.c | 14 ++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index db7d5f55f0..d6b241de42 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -44,6 +44,10 @@ SNE 011100 ..... ..... ..... 00000 101011 @r3 SEQI 011100 rs:5 rt:5 imm:s10 101110 &cmpi SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi +&saa base rt +@saa ...... base:5 rt:5 ................ &saa +SAA 011100 ..... ..... 00000 00000 011000 @saa + &lx base index rd @lx ...... base:5 index:5 rd:5 ...... ..... &lx LWX 011111 ..... ..... ..... 00000 001010 @lx diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index 401c4bd14b..f00692830a 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -161,6 +161,20 @@ static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop) return true; } +static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop) +{ + TCGv_i64 addr = tcg_temp_new_i64(); + TCGv_i64 value = tcg_temp_new_i64(); + TCGv_i64 old = tcg_temp_new_i64(); + MemOp amo = mo_endian(ctx) | mop | MO_ALIGN; + + gen_base_offset_addr(ctx, addr, a->base, 0); + gen_load_gpr(value, a->rt); + tcg_gen_atomic_fetch_add_i64(old, addr, value, ctx->mem_idx, amo); + return true; +} + +TRANS(SAA, trans_saa, MO_32); TRANS(LBX, trans_lx, MO_SB); TRANS(LBUX, trans_lx, MO_UB); TRANS(LHX, trans_lx, MO_SW); -- 2.54.0
