Add explicit decodetree entries and translator bindings for the Octeon CHORD and sparse LLM COP2 selectors. CHORD and LLM use their own COP2 selector window rather than the crypto engine windows covered by the preceding decode patches.
Finish the explicit COP2 selector decode by adding the CP2_Undef fallback so unknown Octeon COP2 selectors raise the expected coprocessor-unusable exception instead of silently taking a generic path. Signed-off-by: James Hilliard <[email protected]> --- target/mips/tcg/octeon.decode | 14 ++++++++++++++ target/mips/tcg/octeon_translate.c | 13 +++++++++++++ 2 files changed, 27 insertions(+) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index cd4fc34d26..0ff8c0d7cd 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -160,6 +160,9 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MF_GFM_RESINP0 010010 00001 rt:5 0000 0010 0101 1010 &cp2 CVM_MF_GFM_RESINP1 010010 00001 rt:5 0000 0010 0101 1011 &cp2 CVM_MF_GFM_POLY 010010 00001 rt:5 0000 0010 0101 1110 &cp2 + CVM_MF_CHORD 010010 00001 rt:5 0000 0100 0000 0000 &cp2 + CVM_MF_LLM_DATA0 010010 00001 rt:5 0000 0100 0000 0010 &cp2 + CVM_MF_LLM_DATA1 010010 00001 rt:5 0000 0100 0000 1010 &cp2 CVM_MT_HSH_DAT0 010010 00101 rt:5 0000 0000 0100 0000 &cp2 CVM_MT_HSH_DAT1 010010 00101 rt:5 0000 0000 0100 0001 &cp2 CVM_MT_HSH_DAT2 010010 00101 rt:5 0000 0000 0100 0010 &cp2 @@ -253,6 +256,16 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_SHA3_XORDAT15 010010 00101 rt:5 0000 0010 1100 1111 &cp2 CVM_MT_SHA3_XORDAT16 010010 00101 rt:5 0000 0010 1101 0000 &cp2 CVM_MT_SHA3_XORDAT17 010010 00101 rt:5 0000 0010 1101 0001 &cp2 + CVM_MT_LLM_READ_ADDR0 010010 00101 rt:5 0000 0100 0000 0000 &cp2 + CVM_MT_LLM_WRITE_ADDR0 010010 00101 rt:5 0000 0100 0000 0001 &cp2 + CVM_MT_LLM_DATA0 010010 00101 rt:5 0000 0100 0000 0010 &cp2 + CVM_MT_LLM_READ64_ADDR0 010010 00101 rt:5 0000 0100 0000 0100 &cp2 + CVM_MT_LLM_WRITE64_ADDR0 010010 00101 rt:5 0000 0100 0000 0101 &cp2 + CVM_MT_LLM_READ_ADDR1 010010 00101 rt:5 0000 0100 0000 1000 &cp2 + CVM_MT_LLM_WRITE_ADDR1 010010 00101 rt:5 0000 0100 0000 1001 &cp2 + CVM_MT_LLM_DATA1 010010 00101 rt:5 0000 0100 0000 1010 &cp2 + CVM_MT_LLM_READ64_ADDR1 010010 00101 rt:5 0000 0100 0000 1100 &cp2 + CVM_MT_LLM_WRITE64_ADDR1 010010 00101 rt:5 0000 0100 0000 1101 &cp2 CVM_MT_CRC_WRITE_LEN 010010 00101 rt:5 0001 0010 0000 0010 &cp2 CVM_MT_CRC_WRITE_DWORD 010010 00101 rt:5 0001 0010 0000 0111 &cp2 CVM_MT_CRC_WRITE_VAR 010010 00101 rt:5 0001 0010 0000 1000 &cp2 @@ -287,4 +300,5 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_HSH_STARTSHA512 010010 00101 rt:5 0100 0010 0100 1111 &cp2 CVM_MT_GFM_XORMUL1 010010 00101 rt:5 0100 0010 0101 1101 &cp2 ] + CP2_Undef 010010 ----- ----- ---- ---- ---- ---- } diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index 0037bd02a8..daaf220a40 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -180,6 +180,9 @@ CP2_MF_I64(CVM_MF_GFM_MUL1, gfm_mul[1]); CP2_MF_I64(CVM_MF_GFM_RESINP0, gfm_resinp[0]); CP2_MF_I64(CVM_MF_GFM_RESINP1, gfm_resinp[1]); CP2_MF_U16(CVM_MF_GFM_POLY, gfm_poly); +CP2_MF_I64(CVM_MF_CHORD, chord); +CP2_MF_I64(CVM_MF_LLM_DATA0, llm_data[0]); +CP2_MF_I64(CVM_MF_LLM_DATA1, llm_data[1]); CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect); CP2_MF_HELPER(CVM_MF_SHA3_DAT24, sha3_dat24); @@ -247,6 +250,8 @@ CP2_MT_I64(CVM_MT_GFM_RESINP0, gfm_resinp[0]); CP2_MT_I64(CVM_MT_GFM_RESINP1, gfm_resinp[1]); CP2_MT_HELPER(CVM_MT_GFM_XOR0, gfm_xor0); CP2_MT_U16(CVM_MT_GFM_POLY, gfm_poly); +CP2_MT_I64(CVM_MT_LLM_DATA0, llm_data[0]); +CP2_MT_I64(CVM_MT_LLM_DATA1, llm_data[1]); CP2_MT_U8(CVM_MT_CRC_WRITE_LEN, crc_len); CP2_MT_U32(CVM_MT_CRC_WRITE_POLYNOMIAL, crc_poly); CP2_MT_U32(CVM_MT_CRC_WRITE_POLYNOMIAL_REFLECT, crc_poly); @@ -335,6 +340,14 @@ CP2_MT_HELPER(CVM_MT_HSH_STARTMD5, hsh_startmd5); CP2_MT_HELPER(CVM_MT_HSH_STARTSHA256, hsh_startsha256); CP2_MT_HELPER(CVM_MT_HSH_STARTSHA, hsh_startsha); CP2_MT_HELPER(CVM_MT_HSH_STARTSHA512, hsh_startsha512); +CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR0, llm_read_addr0); +CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR0, llm_write_addr0); +CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR0, llm_read64_addr0); +CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR0, llm_write64_addr0); +CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR1, llm_read_addr1); +CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR1, llm_write_addr1); +CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR1, llm_read64_addr1); +CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR1, llm_write64_addr1); static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) { -- 2.54.0
