On 20/5/26 12:17, Philippe Mathieu-Daudé wrote:
From: James Hilliard <[email protected]>
SAA atomically adds rt to the naturally aligned 32-bit word at base and
discards the old memory value.
Implement the common SAA/SAAD translator with TCG atomic_fetch_add_i64.
The MemOp selects the word or doubleword transaction size. QEMU only has
one Octeon CPU model today, so keep SAA/SAAD under the existing Octeon
instruction feature bucket instead of adding a finer-grained Octeon+
feature bit.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: James Hilliard <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
---
target/mips/tcg/octeon.decode | 4 ++++
target/mips/tcg/octeon_translate.c | 14 ++++++++++++++
2 files changed, 18 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
