On 20/5/26 12:18, Philippe Mathieu-Daudé wrote:
From: James Hilliard <[email protected]>
Implement the Octeon LA* read-modify-write atomic instruction family:
LAI/LAID, LAD/LADD, LAA/LAAD, LAS/LASD, LAC/LACD, and LAW/LAWD.
These operations are architecturally distinct from SAA/SAAD and are used
by existing Octeon user-mode code for atomic counters, bit operations,
and exchange-style updates.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: James Hilliard <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
---
target/mips/tcg/octeon.decode | 17 +++++++
target/mips/tcg/octeon_translate.c | 75 ++++++++++++++++++++++++++++++
2 files changed, 92 insertions(+)
diff --git a/target/mips/tcg/octeon_translate.c
b/target/mips/tcg/octeon_translate.c
index 684236b1a87..eff46c30a09 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -177,6 +177,68 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp
mop)
TRANS(SAA, trans_saa, MO_32);
TRANS(SAAD, trans_saa, MO_64);
+static bool trans_la_fetch_add(DisasContext *ctx, int base, int add_reg,
+ int rd, int64_t imm, MemOp mop)
+{
+ TCGv_i64 addr = tcg_temp_new_i64();
+ TCGv_i64 value = tcg_temp_new_i64();
+ TCGv_i64 old = tcg_temp_new_i64();
+ MemOp amo = mo_endian(ctx) | mop | MO_ALIGN;
+
+ gen_base_offset_addr(ctx, addr, base, 0);
+
+ if (add_reg >= 0) {
+ gen_load_gpr(value, add_reg);
+ } else {
+ tcg_gen_movi_i64(value, imm);
+ }
+
+ tcg_gen_atomic_fetch_add_i64(old, addr, value, ctx->mem_idx, amo);
+ gen_store_gpr(old, rd);
+ return true;
+}
+
+static bool trans_la_xchg(DisasContext *ctx, int base, int add_reg, int rd,
+ int64_t imm, MemOp mop)
+{
+ TCGv_i64 addr = tcg_temp_new_i64();
+ TCGv_i64 value = tcg_temp_new_i64();
+ TCGv_i64 old = tcg_temp_new_i64();
+ MemOp amo = mo_endian(ctx) | mop | MO_ALIGN;
+
+ gen_base_offset_addr(ctx, addr, base, 0);
+
+ if (add_reg >= 0) {
+ gen_load_gpr(value, add_reg);
+ } else {
+ tcg_gen_movi_i64(value, imm);
+ }
+
+ tcg_gen_atomic_xchg_i64(old, addr, value, ctx->mem_idx, amo);
+ gen_store_gpr(old, rd);
+ return true;
+}
+
+static bool do_la_imm_add(DisasContext *ctx, arg_la *a, int64_t imm, MemOp mop)
+{
+ return trans_la_fetch_add(ctx, a->base, -1, a->rd, imm, mop);
+}
+
+static bool do_la_reg_add(DisasContext *ctx, arg_laa *a, MemOp mop)
+{
+ return trans_la_fetch_add(ctx, a->base, a->add, a->rd, 0, mop);
+}
+
+static bool do_la_imm_xchg(DisasContext *ctx, arg_la *a, int64_t imm, MemOp
mop)
+{
+ return trans_la_xchg(ctx, a->base, -1, a->rd, imm, mop);
+}
+
+static bool do_la_reg_xchg(DisasContext *ctx, arg_laa *a, MemOp mop)
+{
+ return trans_la_xchg(ctx, a->base, a->add, a->rd, 0, mop);
+}
+
static bool trans_ZCB(DisasContext *ctx, arg_ZCB *a)
{
TCGv_i64 addr = tcg_temp_new_i64();
@@ -418,3 +480,16 @@ static bool trans_QMACS(DisasContext *ctx, arg_QMACS *a)
tcg_gen_or_i64(cpu_HI[0], cpu_HI[0], t0);
return true;
}
+
+TRANS(LAI, do_la_imm_add, 1, MO_SL);
+TRANS(LAID, do_la_imm_add, 1, MO_UQ);
+TRANS(LAD, do_la_imm_add, -1, MO_SL);
+TRANS(LADD, do_la_imm_add, -1, MO_UQ);
+TRANS(LAA, do_la_reg_add, MO_SL);
+TRANS(LAAD, do_la_reg_add, MO_UQ);
+TRANS(LAS, do_la_imm_xchg, -1, MO_SL);
+TRANS(LASD, do_la_imm_xchg, -1, MO_UQ);
+TRANS(LAC, do_la_imm_xchg, 0, MO_SL);
+TRANS(LACD, do_la_imm_xchg, 0, MO_UQ);
+TRANS(LAW, do_la_reg_xchg, MO_SL);
+TRANS(LAWD, do_la_reg_xchg, MO_UQ);
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Alternatively passing the atomic function by argument to TRANS():
-- >8 --
+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_va, TCGv_i64, TCGArg, MemOp);
+
+static bool do_atomic_ld(DisasContext *ctx, AtomicThreeOpFn *atomic_fn,
+ int base, int add_reg, int rd, int64_t imm,
MemOp mop)
+{
+ TCGv_i64 addr = tcg_temp_new_i64();
+ TCGv_i64 value = tcg_temp_new_i64();
+ TCGv_i64 old = tcg_temp_new_i64();
+ MemOp amo = mo_endian(ctx) | mop | MO_ALIGN;
+
+ gen_base_offset_addr(ctx, addr, base, 0);
+
+ if (add_reg >= 0) {
+ gen_load_gpr(value, add_reg);
+ } else {
+ tcg_gen_movi_i64(value, imm);
+ }
+
+ atomic_fn(old, addr, value, ctx->mem_idx, amo);
+ gen_store_gpr(old, rd);
+ return true;
+}
+
+static bool do_atomic_la(DisasContext *ctx, arg_la *a, AtomicThreeOpFn *fn,
+ int64_t imm, MemOp mop)
+{
+ return do_atomic_ld(ctx, fn, a->base, -1, a->rd, imm, mop);
+}
+
+static bool do_atomic_laa(DisasContext *ctx, arg_laa *a,
AtomicThreeOpFn *fn,
+ int64_t imm, MemOp mop)
+{
+ return do_atomic_ld(ctx, fn, a->base, a->add, a->rd, imm, mop);
+}
+
+TRANS(LAI, do_atomic_la, tcg_gen_atomic_fetch_add_i64, 1, MO_SL);
+TRANS(LAID, do_atomic_la, tcg_gen_atomic_fetch_add_i64, 1, MO_UQ);
+TRANS(LAD, do_atomic_la, tcg_gen_atomic_fetch_add_i64, -1, MO_SL);
+TRANS(LADD, do_atomic_la, tcg_gen_atomic_fetch_add_i64, -1, MO_UQ);
+TRANS(LAA, do_atomic_laa, tcg_gen_atomic_fetch_add_i64, 0, MO_SL);
+TRANS(LAAD, do_atomic_laa, tcg_gen_atomic_fetch_add_i64, 0, MO_UQ);
+TRANS(LAS, do_atomic_la, tcg_gen_atomic_xchg_i64, -1, MO_SL);
+TRANS(LASD, do_atomic_la, tcg_gen_atomic_xchg_i64, -1, MO_UQ);
+TRANS(LAC, do_atomic_la, tcg_gen_atomic_xchg_i64, 0, MO_SL);
+TRANS(LACD, do_atomic_la, tcg_gen_atomic_xchg_i64, 0, MO_UQ);
+TRANS(LAW, do_atomic_laa, tcg_gen_atomic_xchg_i64, 0, MO_SL);
+TRANS(LAWD, do_atomic_laa, tcg_gen_atomic_xchg_i64, 0, MO_UQ);
---
