Register machines able to run in qemu-system-riscv32, qemu-system-riscv64, or both.
Reviewed-by: Pierrick Bouvier <[email protected]> Signed-off-by: Anton Johansson <[email protected]> --- hw/riscv/boston-aia.c | 3 ++- hw/riscv/microblaze-v-generic.c | 3 ++- hw/riscv/microchip_pfsoc.c | 2 ++ hw/riscv/opentitan.c | 2 ++ hw/riscv/shakti_c.c | 2 ++ hw/riscv/sifive_e.c | 2 ++ hw/riscv/sifive_u.c | 2 ++ hw/riscv/spike.c | 2 ++ hw/riscv/virt.c | 3 +++ hw/riscv/xiangshan_kmh.c | 2 ++ 10 files changed, 21 insertions(+), 2 deletions(-) diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c index b90da096ea..965d0f5699 100644 --- a/hw/riscv/boston-aia.c +++ b/hw/riscv/boston-aia.c @@ -18,6 +18,7 @@ #include "hw/ide/ahci-pci.h" #include "hw/core/loader.h" #include "hw/riscv/cps.h" +#include "hw/riscv/machines-qom.h" #include "hw/pci-host/xilinx-pcie.h" #include "hw/core/qdev-properties.h" #include "qapi/error.h" @@ -473,4 +474,4 @@ static void boston_mach_class_init(MachineClass *mc) mc->default_cpu_type = TYPE_RISCV_CPU_MIPS_P8700; } -DEFINE_MACHINE("boston-aia", boston_mach_class_init) +DEFINE_MACHINE_RISCV64("boston-aia", boston_mach_class_init) diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c index b0494b1ac5..d33ac39a68 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -25,6 +25,7 @@ #include "system/address-spaces.h" #include "hw/char/xilinx_uartlite.h" #include "hw/misc/unimp.h" +#include "hw/riscv/machines-qom.h" #define LMB_BRAM_SIZE (128 * KiB) #define MEMORY_BASEADDR 0x80000000 @@ -186,4 +187,4 @@ static void mb_v_generic_machine_init(MachineClass *mc) mc->default_cpus = 1; } -DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init) +DEFINE_MACHINE_RISCV32_64("amd-microblaze-v-generic", mb_v_generic_machine_init) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 743f31f005..5e48a29708 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -49,6 +49,7 @@ #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/machines-qom.h" #include "hw/riscv/microchip_pfsoc.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -751,6 +752,7 @@ static const TypeInfo microchip_icicle_kit_machine_typeinfo = { .class_init = microchip_icicle_kit_machine_class_init, .instance_init = microchip_icicle_kit_machine_instance_init, .instance_size = sizeof(MicrochipIcicleKitState), + .interfaces = riscv64_machine_interfaces, }; static void microchip_icicle_kit_machine_init_register_types(void) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 309125e854..c8b2f028f2 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -26,6 +26,7 @@ #include "hw/core/boards.h" #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "qemu/units.h" #include "system/system.h" #include "system/address-spaces.h" @@ -335,6 +336,7 @@ static const TypeInfo open_titan_types[] = { .parent = TYPE_MACHINE, .instance_size = sizeof(OpenTitanState), .class_init = opentitan_machine_class_init, + .interfaces = riscv32_machine_interfaces, } }; diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 49a39b3021..64207c8d00 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "hw/core/boards.h" #include "hw/riscv/shakti_c.h" +#include "hw/riscv/machines-qom.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/intc/sifive_plic.h" @@ -92,6 +93,7 @@ static const TypeInfo shakti_c_machine_type_info = { .class_init = shakti_c_machine_class_init, .instance_init = shakti_c_machine_instance_init, .instance_size = sizeof(ShaktiCMachineState), + .interfaces = riscv64_machine_interfaces, }; static void shakti_c_machine_type_info_register(void) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 1acfea4966..71925583bd 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -40,6 +40,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_e.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/sifive_uart.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -167,6 +168,7 @@ static const TypeInfo sifive_e_machine_typeinfo = { .class_init = sifive_e_machine_class_init, .instance_init = sifive_e_machine_instance_init, .instance_size = sizeof(SiFiveEState), + .interfaces = riscv32_64_machine_interfaces, }; static void sifive_e_machine_init_register_types(void) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7ec67b2565..6a637e3b86 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -51,6 +51,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/sifive_uart.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -742,6 +743,7 @@ static const TypeInfo sifive_u_machine_typeinfo = { .class_init = sifive_u_machine_class_init, .instance_init = sifive_u_machine_instance_init, .instance_size = sizeof(SiFiveUState), + .interfaces = riscv32_64_machine_interfaces, }; static void sifive_u_machine_init_register_types(void) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 35c696f891..08ef291b6b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -33,6 +33,7 @@ #include "hw/riscv/spike.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/riscv_htif.h" #include "hw/intc/riscv_aclint.h" #include "chardev/char.h" @@ -366,6 +367,7 @@ static const TypeInfo spike_machine_typeinfo = { .class_init = spike_machine_class_init, .instance_init = spike_machine_instance_init, .instance_size = sizeof(SpikeState), + .interfaces = riscv32_64_machine_interfaces, }; static void spike_machine_init_register_types(void) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 315049bc86..39caf37c01 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -36,6 +36,7 @@ #include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/riscv/numa.h" #include "kvm/kvm_riscv.h" #include "hw/firmware/smbios.h" @@ -2001,6 +2002,8 @@ static const TypeInfo virt_machine_typeinfo = { .instance_size = sizeof(RISCVVirtState), .interfaces = (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_TARGET_RISCV32_MACHINE }, + { TYPE_TARGET_RISCV64_MACHINE }, { } }, }; diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 436e51c1c5..76417ba7ab 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -41,6 +41,7 @@ #include "hw/riscv/boot.h" #include "hw/riscv/xiangshan_kmh.h" #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/machines-qom.h" #include "system/system.h" static const MemMapEntry xiangshan_kmh_memmap[] = { @@ -211,6 +212,7 @@ static const TypeInfo xiangshan_kmh_machine_info = { .parent = TYPE_MACHINE, .instance_size = sizeof(XiangshanKmhState), .class_init = xiangshan_kmh_machine_class_init, + .interfaces = riscv64_machine_interfaces, }; static void xiangshan_kmh_machine_register_types(void) -- 2.52.0
