Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Anton Johansson <[email protected]>
---
hw/riscv/meson.build | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 533472e22a..8ea5b098eb 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -1,21 +1,21 @@
-riscv_ss = ss.source_set()
-riscv_ss.add(files('boot.c'))
-riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
-riscv_ss.add(files('riscv_hart.c'))
-riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
-riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
-riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
-riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true:
files('microchip_pfsoc.c'))
-riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
-riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files(
+riscv_common_ss = ss.source_set()
+riscv_common_ss.add(files('boot.c'))
+riscv_common_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
+riscv_common_ss.add(files('riscv_hart.c'))
+riscv_common_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
+riscv_common_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
+riscv_common_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
+riscv_common_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
+riscv_common_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
+riscv_common_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
+riscv_common_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true:
files('microchip_pfsoc.c'))
+riscv_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
+riscv_common_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files(
'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c',
'riscv-iommu-hpm.c'))
-riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true:
files('microblaze-v-generic.c'))
-riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true:
files('xiangshan_kmh.c'))
+riscv_common_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true:
files('microblaze-v-generic.c'))
+riscv_common_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true:
files('xiangshan_kmh.c'))
-riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c'))
-riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'))
+riscv_common_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c'))
+riscv_common_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true:
files('boston-aia.c'))
-hw_arch += {'riscv': riscv_ss}
+hw_common_arch += {'riscv': riscv_common_ss}
--
2.52.0
