On Thu, May 28, 2026 at 6:16 AM Philippe Mathieu-Daudé <[email protected]> wrote: > > From: Djordje Todorovic <[email protected]> > > Add a big_endian field to RISCVCPUConfig and wire it into the CPU > reset path. When cfg.big_endian is set, riscv_cpu_reset_hold() > writes 1 into the MSTATUS MBE/SBE/UBE fields using set_field(); > otherwise it writes 0. This makes the reset value deterministic on > both cold and warm reset. > > This models fixed-endian harts, not mixed-endian implementations where > the guest can toggle MBE/SBE/UBE at runtime. The MBE/SBE/UBE bits are > not included in the writable mask of any mstatus/mstatush/sstatus CSR > write path (unchanged by this series), so the value chosen at reset is > effectively hardwired per section 3.1.6.5 of the RISC-V Privileged > Specification. > > The user-facing property and documentation are added in a later patch, > once the full endianness support is in place. > > Signed-off-by: Djordje Todorovic <[email protected]> > Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu_cfg_fields.h.inc | 1 + > target/riscv/cpu.c | 7 +++++++ > 2 files changed, 8 insertions(+) > > diff --git a/target/riscv/cpu_cfg_fields.h.inc > b/target/riscv/cpu_cfg_fields.h.inc > index 734fa079f28..9eb47af0a76 100644 > --- a/target/riscv/cpu_cfg_fields.h.inc > +++ b/target/riscv/cpu_cfg_fields.h.inc > @@ -157,6 +157,7 @@ BOOL_FIELD(ext_xmipscmov) > BOOL_FIELD(ext_xmipslsp) > BOOL_FIELD(ext_xlrbr) > > +BOOL_FIELD(big_endian) > BOOL_FIELD(mmu) > BOOL_FIELD(pmp) > BOOL_FIELD(debug) > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 52f143f1cd4..fef424f2bf9 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -739,6 +739,13 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType > type) > env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1); > } > } > + /* > + * Model fixed-endian harts: MBE/SBE/UBE are initialized from the > + * CPU configuration and are intentionally not writable via status CSRs. > + */ > + env->mstatus = set_field(env->mstatus, MSTATUS_MBE, cpu->cfg.big_endian); > + env->mstatus = set_field(env->mstatus, MSTATUS_SBE, cpu->cfg.big_endian); > + env->mstatus = set_field(env->mstatus, MSTATUS_UBE, cpu->cfg.big_endian); > env->mcause = 0; > env->miclaim = MIP_SGEIP; > env->pc = env->resetvec; > -- > 2.53.0 > >
