x-misa-w controls dynamic writes to misa in the emulated CPU path and is only meaningful when TCG is available. Reject it explicitly outside TCG instead of relying on TCG-only finalize code.
This also covers CONFIG_TCG builds that are running with a non-TCG accelerator. It also rejects CPU models that require writable misa by default when the selected accelerator is not TCG. Signed-off-by: Zephyr Li <[email protected]> --- target/riscv/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 862834b480..8ef72a88b1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -956,6 +956,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); Error *local_err = NULL; + if (cpu->cfg.misa_w) { +#ifdef CONFIG_TCG + if (!tcg_enabled()) { + error_setg(errp, "x-misa-w requires TCG"); + return; + } +#else + error_setg(errp, "x-misa-w requires TCG"); + return; +#endif + } + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); -- 2.43.0
