Several RISC-V source files contain translated-code helpers, decoders, or TCG-only instruction implementations, but are currently part of the common RISC-V source set. This breaks --disable-tcg builds once TCG headers and helpers are unavailable.
After moving common helpers out of TCG-only files, build the remaining TCG-only RISC-V sources only when CONFIG_TCG is enabled. Keep common CSR misa handling from relying on TCG unwind state in no-TCG builds by falling back to env->pc. Drop the stale tcg/tcg.h include from common CPU code so no-TCG builds do not include a TCG-private header. Signed-off-by: Zephyr Li <[email protected]> --- target/riscv/cpu.c | 1 - target/riscv/cpu_helper.c | 6 ++++++ target/riscv/csr.c | 11 +++++++++-- target/riscv/meson.build | 9 ++++++--- 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8ef72a88b1..459e32f4ac 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -36,7 +36,6 @@ #include "system/tcg.h" #include "kvm/kvm_riscv.h" #include "tcg/tcg-cpu.h" -#include "tcg/tcg.h" /* RISC-V CPU definitions */ static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH"; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 752752d520..e53a5d567d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -29,8 +29,10 @@ #include "exec/target_page.h" #include "system/memory.h" #include "instmap.h" +#ifdef CONFIG_TCG #include "tcg/tcg-op.h" #include "accel/tcg/cpu-ops.h" +#endif #include "trace.h" #include "semihosting/common-semi.h" #include "exec/icount.h" @@ -1714,6 +1716,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, return TRANSLATE_SUCCESS; } +#ifdef CONFIG_TCG static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type, bool pmp_violation, bool first_stage, bool two_stage, @@ -1756,6 +1759,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, env->two_stage_lookup = two_stage; env->two_stage_indirect_lookup = two_stage_indirect; } +#endif hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { @@ -1780,6 +1784,7 @@ hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) return phys_addr; } +#ifdef CONFIG_TCG void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, @@ -2004,6 +2009,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return true; } +#endif static target_ulong riscv_transformed_insn(CPURISCVState *env, target_ulong insn, diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 186d32fca8..9a9a148bfe 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2134,15 +2134,22 @@ static RISCVException read_misa(CPURISCVState *env, int csrno, static target_ulong get_next_pc(CPURISCVState *env, uintptr_t ra) { + /* Outside of a running cpu, env contains the next pc. */ + if (ra == 0) { + return env->pc; + } +#ifdef CONFIG_TCG uint64_t data[INSN_START_WORDS]; - /* Outside of a running cpu, env contains the next pc. */ - if (ra == 0 || !cpu_unwind_state_data(env_cpu(env), ra, data)) { + if (!cpu_unwind_state_data(env_cpu(env), ra, data)) { return env->pc; } /* Within unwind data, [0] is pc and [1] is the opcode. */ return data[0] + insn_len(data[1]); +#else + return env->pc; +#endif } static RISCVException write_misa(CPURISCVState *env, int csrno, diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 4c99f2b802..2f86dbd5bf 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -9,7 +9,7 @@ gen = [ ] riscv_ss = ss.source_set() -riscv_ss.add(gen) +riscv_ss.add(when: 'CONFIG_TCG', if_true: gen) riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('common-semi-target.c')) @@ -19,11 +19,14 @@ riscv_ss.add(files( 'cpu-validate.c', 'cpu_helper.c', 'csr.c', - 'fpu_helper.c', 'gdbstub.c', + 'vector_internals.c', +)) + +riscv_ss.add(when: 'CONFIG_TCG', if_true: files( + 'fpu_helper.c', 'op_helper.c', 'vector_helper.c', - 'vector_internals.c', 'bitmanip_helper.c', 'translate.c', 'm128_helper.c', -- 2.43.0
