Move the 'flitmode' property from PCIESlot to PCIEPort. This change allows all the derived ports (PCIe ports or CXL ports) to use this property.
This is a structural refactor only. There is no functional change in existing behavior. Note: This property was added from Davidlohr's BI patch series[1]. [1]: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Shrihari E S <[email protected]> --- hw/pci-bridge/cxl_downstream.c | 6 +++--- hw/pci-bridge/cxl_root_port.c | 6 +++--- hw/pci/pcie.c | 2 +- include/hw/pci/pcie_port.h | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index d1e27994a3..7c7a1d1221 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -118,7 +118,7 @@ static void cxl_dsp_reset(DeviceState *qdev) static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) { - PCIESlot *s = PCIE_SLOT(d); + PCIEPort *p = PCIE_PORT(d); CXLDVSECRegisterLocator *regloc_dvsec; uint8_t *dvsec; int i; @@ -132,7 +132,7 @@ static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ .cap = 0x27, /* Cache, IO, Mem, non-MLD */ .ctrl = 0x02, /* IO always enabled */ - .status = s->flitmode ? 0x6 : 0x26, /* lack of 68B */ + .status = p->flitmode ? 0x6 : 0x26, /* lack of 68B */ .rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */ }; cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, @@ -259,7 +259,7 @@ static const Property cxl_dsp_props[] = { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_16), - DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), }; static void cxl_dsp_class_init(ObjectClass *oc, const void *data) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 0ee18ef5c3..df69c5200f 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -112,7 +112,7 @@ static void latch_registers(CXLRootPort *crp) static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) { - PCIESlot *s = PCIE_SLOT(d); + PCIEPort *p = PCIE_PORT(d); CXLDVSECRegisterLocator *regloc_dvsec; uint8_t *dvsec; int i; @@ -135,7 +135,7 @@ static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ .cap = 0x26, /* IO, Mem, non-MLD */ .ctrl = 0x2, - .status = s->flitmode ? 0x6 : 0x26, /* lack of 68B */ + .status = p->flitmode ? 0x6 : 0x26, /* lack of 68B */ .rcvd_mod_ts_data_phase1 = 0xef, }; cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, @@ -237,7 +237,7 @@ static const Property gen_rp_props[] = { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), - DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), }; static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 1de0b1e4fd..d452199d85 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -217,7 +217,7 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */ } - pcie_cap_fill_lnk(exp_cap, s->width, s->speed, s->flitmode); + pcie_cap_fill_lnk(exp_cap, s->width, s->speed, s->parent_obj.flitmode); } int pcie_cap_init(PCIDevice *dev, uint8_t offset, diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 53cd64c5ed..1bcc734649 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -33,6 +33,7 @@ struct PCIEPort { /*< private >*/ PCIBridge parent_obj; /*< public >*/ + bool flitmode; /* pci express switch port */ uint8_t port; @@ -58,7 +59,6 @@ struct PCIESlot { PCIExpLinkSpeed speed; PCIExpLinkWidth width; - bool flitmode; /* Disable ACS (really for a pcie_root_port) */ bool disable_acs; -- 2.34.1
