Integrate Streamlined Virtual Channel (SVC) capability initialization into the realize() functions of both PCIe and CXL ports. This change ensures that the 'uio_capable' flag is correctly populated in CXL ports during the initialization sequence.
'uio_capable' in CXL ports is responsible for enabling UIO capability in HDM decoder registers. Signed-off-by: Shrihari E S <[email protected]> Signed-off-by: Dongjoo Seo <[email protected]> --- hw/pci-bridge/cxl_downstream.c | 1 + hw/pci-bridge/cxl_root_port.c | 5 +++++ hw/pci-bridge/cxl_upstream.c | 4 ++++ hw/pci-bridge/pcie_root_port.c | 1 + hw/pci-bridge/xio3130_downstream.c | 1 + hw/pci-bridge/xio3130_upstream.c | 1 + 6 files changed, 13 insertions(+) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index e0fa6cfdc4..a9eaeb81bb 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -229,6 +229,7 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &dsp->bar); + pcie_config_uio_svc(d, errp); return; diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 4be2b400f9..eafcf59f83 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -164,6 +164,7 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp) { PCIDevice *pci_dev = PCI_DEVICE(dev); PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); + PCIEPort *p = PCIE_PORT(dev); CXLRootPort *crp = CXL_ROOT_PORT(dev); CXLComponentState *cxl_cstate = &crp->cxl_cstate; ComponentRegisters *cregs = &cxl_cstate->crb; @@ -212,6 +213,10 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp) PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &crp->bar); + rc = pcie_config_uio_svc(pci_dev, errp); + if (p->flitmode && rc >= 0) { + crp->uio_capable = true; + } } static void cxl_rp_reset_hold(Object *obj, ResetType type) diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index a75d10e7b4..f6f5713437 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -411,6 +411,10 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) goto err_cap; } + rc = pcie_config_uio_svc(d, errp); + if (p->flitmode && rc >= 0) { + usp->uio_capable = true; + } return; err_cap: diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 20554bd854..5a74b0e978 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -97,6 +97,7 @@ static void rp_realize(PCIDevice *d, Error **errp) goto err_int; } + pcie_config_uio_svc(d, errp); pcie_cap_arifwd_init(d); pcie_cap_deverr_init(d); pcie_cap_slot_init(d, s); diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index b0b297bb53..cc19fb1213 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -93,6 +93,7 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) if (rc < 0) { goto err_msi; } + pcie_config_uio_svc(d, errp); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); pcie_cap_slot_init(d, s); diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c index 925df5add3..c28339dabe 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -84,6 +84,7 @@ static void xio3130_upstream_realize(PCIDevice *d, Error **errp) if (rc < 0) { goto err_msi; } + pcie_config_uio_svc(d, errp); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); -- 2.34.1
