Relocate 'x-256b-flit' property from cxl_root_port to its parent pcie_root_port so that both can utilize this property.
This is a pure refactor and does not impact any existing behavior. Signed-off-by: Shrihari E S <[email protected]> --- hw/pci-bridge/cxl_root_port.c | 1 - hw/pci-bridge/pcie_root_port.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index df69c5200f..e82685d1ab 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -237,7 +237,6 @@ static const Property gen_rp_props[] = { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), - DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), }; static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index fe3ced5685..eeee24e042 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -152,6 +152,7 @@ static const Property rp_props[] = { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), }; static void rp_instance_post_init(Object *obj) -- 2.34.1
