Re: [PATCH v3 2/5] target/riscv: Support raising misaligned exceptions for scalar loads/stores

[Alistair Francis]

On Tue, Jun 30, 2026 at 8:46 PM <frank.ch...@sifive.com> wrote:
>
> From: Frank Chang <frank.ch...@sifive.com>
>
> When the Zicclsm extension is not enabled, raise misaligned load/store
> exceptions for misaligned accesses from scalar load/store instructions.
>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> Reviewed-by: Max Chou <max.c...@sifive.com>
> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

This patch breaks the `func-riscv64-opensbi` test, which you can run
with `make check-functional-riscv64`

Alistair

> ---
>  target/riscv/insn_trans/trans_rvi.c.inc | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc 
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index e47b16a7fa2..cc1b5dbbadc 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -413,6 +413,9 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp 
> memop)
>      if (ctx->cfg_ptr->ext_zama16b) {
>          memop |= MO_ATOM_WITHIN16;
>      }
> +    if (!ctx->cfg_ptr->ext_zicclsm) {
> +        memop |= MO_ALIGN;
> +    }
>      decode_save_opc(ctx, 0);
>      if (get_xl(ctx) == MXL_RV128) {
>          out = gen_load_i128(ctx, a, memop);
> @@ -524,6 +527,9 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp 
> memop)
>      if (ctx->cfg_ptr->ext_zama16b) {
>          memop |= MO_ATOM_WITHIN16;
>      }
> +    if (!ctx->cfg_ptr->ext_zicclsm) {
> +        memop |= MO_ALIGN;
> +    }
>      decode_save_opc(ctx, 0);
>      if (get_xl(ctx) == MXL_RV128) {
>          return gen_store_i128(ctx, a, memop);
> --
> 2.43.0
>
>