On Mon, Jul 6, 2026 at 1:32 PM Alistair Francis <[email protected]> wrote:
> On Tue, Jun 30, 2026 at 8:46 PM <[email protected]> wrote: > > > > From: Frank Chang <[email protected]> > > > > When the Zicclsm extension is not enabled, raise misaligned load/store > > exceptions for misaligned accesses from scalar load/store instructions. > > > > Signed-off-by: Frank Chang <[email protected]> > > Reviewed-by: Max Chou <[email protected]> > > Reviewed-by: Alistair Francis <[email protected]> > > This patch breaks the `func-riscv64-opensbi` test, which you can run > with `make check-functional-riscv64` > Thanks Alistair, The issue is that we need to place the reset vector data at 8-byte-aligned offsets. Otherwise, QEMU would raise the misaligned load exception as SiFive U doesn't support hardware misaligned access. I've updated SiFive U's reset vector data and sent out the v6 patchset. Regards, Frank Chang > > Alistair > > > --- > > target/riscv/insn_trans/trans_rvi.c.inc | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc > b/target/riscv/insn_trans/trans_rvi.c.inc > > index e47b16a7fa2..cc1b5dbbadc 100644 > > --- a/target/riscv/insn_trans/trans_rvi.c.inc > > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > > @@ -413,6 +413,9 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, > MemOp memop) > > if (ctx->cfg_ptr->ext_zama16b) { > > memop |= MO_ATOM_WITHIN16; > > } > > + if (!ctx->cfg_ptr->ext_zicclsm) { > > + memop |= MO_ALIGN; > > + } > > decode_save_opc(ctx, 0); > > if (get_xl(ctx) == MXL_RV128) { > > out = gen_load_i128(ctx, a, memop); > > @@ -524,6 +527,9 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, > MemOp memop) > > if (ctx->cfg_ptr->ext_zama16b) { > > memop |= MO_ATOM_WITHIN16; > > } > > + if (!ctx->cfg_ptr->ext_zicclsm) { > > + memop |= MO_ALIGN; > > + } > > decode_save_opc(ctx, 0); > > if (get_xl(ctx) == MXL_RV128) { > > return gen_store_i128(ctx, a, memop); > > -- > > 2.43.0 > > > > >
