From: Richard Henderson <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
---
target/arm/cpu-features.h | 5 +++++
target/arm/tcg/fp8_helper.c | 16 ++++++++++++++++
target/arm/tcg/helper-fp8-defs.h | 1 +
target/arm/tcg/sme.decode | 3 +++
target/arm/tcg/translate-sme.c | 2 ++
5 files changed, 27 insertions(+)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index e577880ab0..29b4f99aeb 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -1827,6 +1827,11 @@ static inline bool
isar_feature_aa64_sme_mop4_f8f32(const ARMISARegisters *id)
return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_f8f32(id);
}
+static inline bool isar_feature_aa64_sme_mop4_f8f16(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_f8f16(id);
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c
index f899a6cbf7..4b046f5f26 100644
--- a/target/arm/tcg/fp8_helper.c
+++ b/target/arm/tcg/fp8_helper.c
@@ -989,3 +989,19 @@ void HELPER(sme_fmop4a_sb)(void *vza, void *vzn, void *vzm,
FP8MulContext ctx = fp8_mul_start(env, -1);
sme_mop4(vza, vzn, vzm, &ctx, desc, sizeof(float32), inner_fmop4a_sb);
}
+
+static void inner_fmop4a_hb(void *vd, void *vn, void *vm, void *vinfo)
+{
+ float16 *d = vd;
+ uint16_t *n = vn, *m = vm;
+ FP8MulContext *ctx = vinfo;
+
+ *d = f8dotadd_h(*n, *m, 2, *d, ctx);
+}
+
+void HELPER(sme_fmop4a_hb)(void *vza, void *vzn, void *vzm,
+ CPUArchState *env, uint32_t desc)
+{
+ FP8MulContext ctx = fp8_mul_start(env, 0xf);
+ sme_mop4(vza, vzn, vzm, &ctx, desc, sizeof(float16), inner_fmop4a_hb);
+}
diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h
index 47f35a82dc..dedbd8541c 100644
--- a/target/arm/tcg/helper-fp8-defs.h
+++ b/target/arm/tcg/helper-fp8-defs.h
@@ -46,3 +46,4 @@ DEF_HELPER_FLAGS_5(sme_fvdot_idx_sb, TCG_CALL_NO_RWG, void,
ptr, ptr, ptr, env,
DEF_HELPER_FLAGS_5(sme_fvdot_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,
env, i32)
DEF_HELPER_FLAGS_5(sme_fmop4a_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
i32)
+DEF_HELPER_FLAGS_5(sme_fmop4a_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
i32)
diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode
index b8b507d8fb..4b7a99e203 100644
--- a/target/arm/tcg/sme.decode
+++ b/target/arm/tcg/sme.decode
@@ -1101,6 +1101,8 @@ LUTI4_s_4b 1100 0000 1001 101 1 00 00 00 ....0
zd:5 \
@mop4_o3 .... .... ... m:1 .... .... .. n:1 ... . s:1 . zad:3 \
&mop4 zm=%mop4_zm zn=%mop4_zn
+@mop4_o1_s0 .... .... ... m:1 .... .... .. n:1 ... . .... zad:1 \
+ &mop4 zm=%mop4_zm zn=%mop4_zn s=0
@mop4_o2_s0 .... .... ... m:1 .... .... .. n:1 ... . ... zad:2 \
&mop4 zm=%mop4_zm zn=%mop4_zn s=0
@@ -1113,3 +1115,4 @@ BFMOP4_sh 1000 0001 000. ...0 0000 00.. ..0. 00..
@mop4_o2
FMOP4_sh 1000 0001 001. ...0 0000 00.. ..0. 00.. @mop4_o2
FMOP4A_sb 1000 0000 001. ...0 0000 00.. ..00 00.. @mop4_o2_s0
+FMOP4A_hb 1000 0000 001. ...0 0000 00.. ..00 100. @mop4_o1_s0
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 386ded1b90..b198c7c855 100644
--- a/target/arm/tcg/translate-sme.c
+++ b/target/arm/tcg/translate-sme.c
@@ -2090,3 +2090,5 @@ static bool do_mop4_fp8(DisasContext *s, arg_mop4 *a,
MemOp esz,
TRANS_FEAT(FMOP4A_sb, aa64_sme_mop4_f8f32,
do_mop4_fp8, a, MO_32, gen_helper_sme_fmop4a_sb)
+TRANS_FEAT(FMOP4A_hb, aa64_sme_mop4_f8f16,
+ do_mop4_fp8, a, MO_16, gen_helper_sme_fmop4a_hb)
--
2.43.0
