Currently we handle cp15.nsacr with raw bit numbers in the few places we need to work with it. We're about to add some more uses of this field, so define its fields with the FIELD macro and use the macros in the places that were previously using bit numbers.
Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-id: [email protected] --- target/arm/cpu.c | 2 +- target/arm/helper.c | 10 +++++----- target/arm/internals.h | 8 ++++++++ 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 62335b8294..787e4dc7ab 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -779,7 +779,7 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) /* Put CPU into non-secure state */ env->cp15.scr_el3 |= SCR_NS; /* Set NSACR.{CP11,CP10} so NS can access the FPU */ - env->cp15.nsacr |= 3 << 10; + env->cp15.nsacr |= R_NSACR_CP10_MASK | R_NSACR_CP11_MASK; } if (have_el2 && target_el < 2) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 93e3d8b575..af45234ad2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -590,7 +590,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. */ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + !arm_is_secure(env) && !FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { mask = R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; value = (value & ~mask) | (env->cp15.cpacr_el1 & mask); } @@ -607,7 +607,7 @@ static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) uint64_t value = env->cp15.cpacr_el1; if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + !arm_is_secure(env) && !FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { value = ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); } return value; @@ -4105,7 +4105,7 @@ static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. */ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + !arm_is_secure(env) && !FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { uint64_t mask = R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; value = (value & ~mask) | (env->cp15.cptr_el[2] & mask); } @@ -4121,7 +4121,7 @@ static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) uint64_t value = env->cp15.cptr_el[2]; if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + !arm_is_secure(env) && !FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { value |= R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; } return value; @@ -10075,7 +10075,7 @@ int fp_exception_el(CPUARMState *env, int cur_el) */ if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && cur_el <= 2 && !arm_is_secure_below_el3(env))) { - if (!extract32(env->cp15.nsacr, 10, 1)) { + if (!FIELD_EX32(env->cp15.nsacr, NSACR, CP10)) { /* FP insns act as UNDEF */ return cur_el == 2 ? 2 : 1; } diff --git a/target/arm/internals.h b/target/arm/internals.h index fcce3804f3..a50290383d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -135,6 +135,14 @@ FIELD(CPACR_EL1, FPEN, 20, 2) FIELD(CPACR_EL1, SMEN, 24, 2) FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ +/* Bit definitions for NSACR (AArch32 only) */ +FIELD(NSACR, CP10, 10, 1) +FIELD(NSACR, CP11, 11, 1) +FIELD(NSACR, NSD32DIS, 14, 1) /* v7; RES0 in v8 */ +FIELD(NSACR, NSASEDIS, 15, 1) +FIELD(NSACR, RFR, 19, 1) /* v7; RES0 in v8 */ +FIELD(NSACR, NSTRCDIS, 20, 1) + /* Bit definitions for HCPTR (AArch32 only) */ FIELD(HCPTR, TCP10, 10, 1) FIELD(HCPTR, TCP11, 11, 1) -- 2.43.0
