Signed-off-by: Molly Chen <[email protected]>
---
target/riscv/helper.h | 8 ++++++++
target/riscv/insn32.decode | 12 ++++++++++++
target/riscv/tcg/insn_trans/trans_rvp.c.inc | 8 ++++++++
target/riscv/tcg/psimd_helper.c | 17 +++++++++++++++++
4 files changed, 45 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 48604d91a79..638c7b0629d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1680,3 +1680,11 @@ DEF_HELPER_4(maccsu_w11, i64, env, i64, i64, i64)
DEF_HELPER_4(maccu_w00, i64, env, i64, i64, i64)
DEF_HELPER_4(maccu_w01, i64, env, i64, i64, i64)
DEF_HELPER_4(maccu_w11, i64, env, i64, i64, i64)
+
+/* Packed SIMD - Q-Format Multiplication Operations */
+DEF_HELPER_3(pmulq_h, tl, env, tl, tl)
+DEF_HELPER_3(pmulqr_h, tl, env, tl, tl)
+DEF_HELPER_3(pmulq_w, i64, env, i64, i64)
+DEF_HELPER_3(pmulqr_w, i64, env, i64, i64)
+DEF_HELPER_3(mulq, i32, env, i32, i32)
+DEF_HELPER_3(mulqr, i32, env, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a9b407e43e2..9c50a4dbf52 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1522,3 +1522,15 @@ maccsu_w11 11111 11 ..... ..... 011 ..... 0111011 @r
maccu_w00 10101 11 ..... ..... 011 ..... 0111011 @r
maccu_w01 10111 11 ..... ..... 001 ..... 0111011 @r
maccu_w11 10111 11 ..... ..... 011 ..... 0111011 @r
+
+# Packed SIMD - Q-Format Multiplication Operations
+pmulq_h 11010 00 ..... ..... 111 ..... 0111011 @r
+pmulqr_h 11010 10 ..... ..... 111 ..... 0111011 @r
+{
+ mulq 11010 01 ..... ..... 111 ..... 0111011 @r
+ pmulq_w 11010 01 ..... ..... 111 ..... 0111011 @r
+}
+{
+ mulqr 11010 11 ..... ..... 111 ..... 0111011 @r
+ pmulqr_w 11010 11 ..... ..... 111 ..... 0111011 @r
+}
diff --git a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
index 5a30c49016f..3535f71de88 100644
--- a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
@@ -826,3 +826,11 @@ GEN_SIMD_TRANS_ACC_64(maccu_w00)
GEN_SIMD_TRANS_ACC_64(maccu_w01)
GEN_SIMD_TRANS_ACC_64(maccu_w11)
+/* Packed SIMD - Q-Format Multiplication Operations */
+GEN_SIMD_TRANS_VXSAT(pmulq_h)
+GEN_SIMD_TRANS_VXSAT(pmulqr_h)
+GEN_SIMD_TRANS_64_VXSAT(pmulq_w)
+GEN_SIMD_TRANS_64_VXSAT(pmulqr_w)
+GEN_SIMD_TRANS_32_VXSAT(mulq)
+GEN_SIMD_TRANS_32_VXSAT(mulqr)
+
diff --git a/target/riscv/tcg/psimd_helper.c b/target/riscv/tcg/psimd_helper.c
index 91a3aac3ebb..11ca17576be 100644
--- a/target/riscv/tcg/psimd_helper.c
+++ b/target/riscv/tcg/psimd_helper.c
@@ -2638,3 +2638,20 @@ GEN_PSIMD_MUL_ACC_INDEXED(maccu_w11, uint64_t, uint32_t,
uint32_t,
EXTRACT64, INSERT64, ELEMS_D, 0, 1, 1,
PSIMD_MUL_U64)
+/* Q-Format Multiplication Operations */
+
+GEN_PSIMD_QMUL(pmulq_h, target_ulong, int16_t, int32_t, uint16_t,
+ EXTRACT16, INSERT16, ELEMS_H, 15, 0, INT16_MIN, INT16_MAX)
+GEN_PSIMD_QMUL(pmulqr_h, target_ulong, int16_t, int32_t, uint16_t,
+ EXTRACT16, INSERT16, ELEMS_H, 15, 1 << 14, INT16_MIN,
+ INT16_MAX)
+GEN_PSIMD_QMUL(pmulq_w, uint64_t, int32_t, int64_t, uint32_t,
+ EXTRACT32, INSERT32, ELEMS_W, 31, 0, INT32_MIN, INT32_MAX)
+GEN_PSIMD_QMUL(pmulqr_w, uint64_t, int32_t, int64_t, uint32_t,
+ EXTRACT32, INSERT32, ELEMS_W, 31, 1LL << 30, INT32_MIN,
+ INT32_MAX)
+GEN_PSIMD_QMUL(mulq, uint32_t, int32_t, int64_t, uint32_t,
+ EXTRACT32, INSERT32, ELEMS_W, 31, 0, INT32_MIN, INT32_MAX)
+GEN_PSIMD_QMUL(mulqr, uint32_t, int32_t, int64_t, uint32_t,
+ EXTRACT32, INSERT32, ELEMS_W, 31, 1LL << 30, INT32_MIN,
+ INT32_MAX)
--
2.34.1
