Signed-off-by: Molly Chen <[email protected]>
---
target/riscv/helper.h | 63 +++++++
target/riscv/insn32.decode | 93 ++++++++++
target/riscv/tcg/insn_trans/trans_rvp.c.inc | 63 +++++++
target/riscv/tcg/psimd_helper.c | 184 ++++++++++++++++++++
4 files changed, 403 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f83af437d40..f06f40b1284 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1561,3 +1561,66 @@ DEF_HELPER_3(pnclipup_w, i64, env, i64, i64)
/* Packed SIMD - Count Leading Operations */
DEF_HELPER_2(cls, tl, env, tl)
DEF_HELPER_2(clsw, i64, env, i64)
+
+/* Packed SIMD - Pure Multiplication Operations */
+DEF_HELPER_3(pmulh_h, tl, env, tl, tl)
+DEF_HELPER_3(pmulhsu_h, tl, env, tl, tl)
+DEF_HELPER_3(pmulhu_h, tl, env, tl, tl)
+DEF_HELPER_3(pmulhr_h, tl, env, tl, tl)
+DEF_HELPER_3(pmulhrsu_h, tl, env, tl, tl)
+DEF_HELPER_3(pmulhru_h, tl, env, tl, tl)
+DEF_HELPER_3(pmulh_w, i64, env, i64, i64)
+DEF_HELPER_3(pmulhr_w, i64, env, i64, i64)
+DEF_HELPER_3(pmulhsu_w, i64, env, i64, i64)
+DEF_HELPER_3(pmulhrsu_w, i64, env, i64, i64)
+DEF_HELPER_3(pmulhu_w, i64, env, i64, i64)
+DEF_HELPER_3(pmulhru_w, i64, env, i64, i64)
+DEF_HELPER_3(mulhr, i32, env, i32, i32)
+DEF_HELPER_3(mulhrsu, i32, env, i32, i32)
+DEF_HELPER_3(mulhru, i32, env, i32, i32)
+DEF_HELPER_3(pmulh_h_b0, tl, env, tl, tl)
+DEF_HELPER_3(pmulh_h_b1, tl, env, tl, tl)
+DEF_HELPER_3(pmulhsu_h_b0, tl, env, tl, tl)
+DEF_HELPER_3(pmulhsu_h_b1, tl, env, tl, tl)
+DEF_HELPER_3(mulh_h0, i32, env, i32, i32)
+DEF_HELPER_3(mulh_h1, i32, env, i32, i32)
+DEF_HELPER_3(mulhsu_h0, i32, env, i32, i32)
+DEF_HELPER_3(mulhsu_h1, i32, env, i32, i32)
+DEF_HELPER_3(pmulh_w_h0, i64, env, i64, i64)
+DEF_HELPER_3(pmulh_w_h1, i64, env, i64, i64)
+DEF_HELPER_3(pmulhsu_w_h0, i64, env, i64, i64)
+DEF_HELPER_3(pmulhsu_w_h1, i64, env, i64, i64)
+DEF_HELPER_3(pmul_h_b00, tl, env, tl, tl)
+DEF_HELPER_3(pmul_h_b01, tl, env, tl, tl)
+DEF_HELPER_3(pmul_h_b11, tl, env, tl, tl)
+DEF_HELPER_3(pmulsu_h_b00, tl, env, tl, tl)
+DEF_HELPER_3(pmulsu_h_b11, tl, env, tl, tl)
+DEF_HELPER_3(pmulu_h_b00, tl, env, tl, tl)
+DEF_HELPER_3(pmulu_h_b01, tl, env, tl, tl)
+DEF_HELPER_3(pmulu_h_b11, tl, env, tl, tl)
+DEF_HELPER_3(pmul_w_h00, i64, env, i64, i64)
+DEF_HELPER_3(pmul_w_h01, i64, env, i64, i64)
+DEF_HELPER_3(pmul_w_h11, i64, env, i64, i64)
+DEF_HELPER_3(pmulsu_w_h00, i64, env, i64, i64)
+DEF_HELPER_3(pmulsu_w_h11, i64, env, i64, i64)
+DEF_HELPER_3(pmulu_w_h00, i64, env, i64, i64)
+DEF_HELPER_3(pmulu_w_h01, i64, env, i64, i64)
+DEF_HELPER_3(pmulu_w_h11, i64, env, i64, i64)
+DEF_HELPER_3(pm2sadd_h, tl, env, tl, tl)
+DEF_HELPER_3(pm2sadd_hx, tl, env, tl, tl)
+DEF_HELPER_3(mul_h00, i32, env, i32, i32)
+DEF_HELPER_3(mul_h01, i32, env, i32, i32)
+DEF_HELPER_3(mul_h11, i32, env, i32, i32)
+DEF_HELPER_3(mulsu_h00, i32, env, i32, i32)
+DEF_HELPER_3(mulsu_h11, i32, env, i32, i32)
+DEF_HELPER_3(mulu_h00, i32, env, i32, i32)
+DEF_HELPER_3(mulu_h01, i32, env, i32, i32)
+DEF_HELPER_3(mulu_h11, i32, env, i32, i32)
+DEF_HELPER_3(mul_w00, i64, env, i64, i64)
+DEF_HELPER_3(mul_w01, i64, env, i64, i64)
+DEF_HELPER_3(mul_w11, i64, env, i64, i64)
+DEF_HELPER_3(mulsu_w00, i64, env, i64, i64)
+DEF_HELPER_3(mulsu_w11, i64, env, i64, i64)
+DEF_HELPER_3(mulu_w00, i64, env, i64, i64)
+DEF_HELPER_3(mulu_w01, i64, env, i64, i64)
+DEF_HELPER_3(mulu_w11, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 14dab4cb641..cc0cc35fe24 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1337,3 +1337,96 @@ pnclipup_w 1000011 ..... ..... 010 ..... 0111011 @r
# Packed SIMD - Count Leading Operations
cls 01100 0000011 ..... 001 ..... 0010011 @r2
clsw 01100 0000011 ..... 001 ..... 0011011 @r2
+
+# Packed SIMD - Pure Multiplication Operations
+pmulh_h 10000 00 ..... ..... 111 ..... 0111011 @r
+pmulhsu_h 11000 00 ..... ..... 111 ..... 0111011 @r
+pmulhu_h 10010 00 ..... ..... 111 ..... 0111011 @r
+pmulhr_h 10000 10 ..... ..... 111 ..... 0111011 @r
+pmulhrsu_h 11000 10 ..... ..... 111 ..... 0111011 @r
+pmulhru_h 10010 10 ..... ..... 111 ..... 0111011 @r
+pmulh_w 10000 01 ..... ..... 111 ..... 0111011 @r
+{
+ mulhr 10000 11 ..... ..... 111 ..... 0111011 @r
+ pmulhr_w 10000 11 ..... ..... 111 ..... 0111011 @r
+}
+pmulhsu_w 11000 01 ..... ..... 111 ..... 0111011 @r
+{
+ mulhrsu 11000 11 ..... ..... 111 ..... 0111011 @r
+ pmulhrsu_w 11000 11 ..... ..... 111 ..... 0111011 @r
+}
+pmulhu_w 10010 01 ..... ..... 111 ..... 0111011 @r
+{
+ mulhru 10010 11 ..... ..... 111 ..... 0111011 @r
+ pmulhru_w 10010 11 ..... ..... 111 ..... 0111011 @r
+}
+pmulh_h_b0 10100 00 ..... ..... 111 ..... 0111011 @r
+pmulh_h_b1 10110 00 ..... ..... 111 ..... 0111011 @r
+pmulhsu_h_b0 10100 10 ..... ..... 111 ..... 0111011 @r
+pmulhsu_h_b1 10110 10 ..... ..... 111 ..... 0111011 @r
+{
+ mulh_h0 10100 01 ..... ..... 111 ..... 0111011 @r
+ pmulh_w_h0 10100 01 ..... ..... 111 ..... 0111011 @r
+}
+{
+ mulh_h1 10110 01 ..... ..... 111 ..... 0111011 @r
+ pmulh_w_h1 10110 01 ..... ..... 111 ..... 0111011 @r
+}
+{
+ mulhsu_h0 10100 11 ..... ..... 111 ..... 0111011 @r
+ pmulhsu_w_h0 10100 11 ..... ..... 111 ..... 0111011 @r
+}
+{
+ mulhsu_h1 10110 11 ..... ..... 111 ..... 0111011 @r
+ pmulhsu_w_h1 10110 11 ..... ..... 111 ..... 0111011 @r
+}
+pmul_h_b00 10000 00 ..... ..... 011 ..... 0111011 @r
+pmul_h_b01 10010 00 ..... ..... 001 ..... 0111011 @r
+pmul_h_b11 10010 00 ..... ..... 011 ..... 0111011 @r
+pmulsu_h_b00 11100 00 ..... ..... 011 ..... 0111011 @r
+pmulsu_h_b11 11110 00 ..... ..... 011 ..... 0111011 @r
+pmulu_h_b00 10100 00 ..... ..... 011 ..... 0111011 @r
+pmulu_h_b01 10110 00 ..... ..... 001 ..... 0111011 @r
+pmulu_h_b11 10110 00 ..... ..... 011 ..... 0111011 @r
+{
+ mul_h00 10000 01 ..... ..... 011 ..... 0111011 @r
+ pmul_w_h00 10000 01 ..... ..... 011 ..... 0111011 @r
+}
+{
+ mul_h01 10010 01 ..... ..... 001 ..... 0111011 @r
+ pmul_w_h01 10010 01 ..... ..... 001 ..... 0111011 @r
+}
+{
+ mul_h11 10010 01 ..... ..... 011 ..... 0111011 @r
+ pmul_w_h11 10010 01 ..... ..... 011 ..... 0111011 @r
+}
+{
+ mulsu_h00 11100 01 ..... ..... 011 ..... 0111011 @r
+ pmulsu_w_h00 11100 01 ..... ..... 011 ..... 0111011 @r
+}
+{
+ mulsu_h11 11110 01 ..... ..... 011 ..... 0111011 @r
+ pmulsu_w_h11 11110 01 ..... ..... 011 ..... 0111011 @r
+}
+{
+ mulu_h00 10100 01 ..... ..... 011 ..... 0111011 @r
+ pmulu_w_h00 10100 01 ..... ..... 011 ..... 0111011 @r
+}
+{
+ mulu_h01 10110 01 ..... ..... 001 ..... 0111011 @r
+ pmulu_w_h01 10110 01 ..... ..... 001 ..... 0111011 @r
+}
+{
+ mulu_h11 10110 01 ..... ..... 011 ..... 0111011 @r
+ pmulu_w_h11 10110 01 ..... ..... 011 ..... 0111011 @r
+}
+pm2sadd_h 11000 10 ..... ..... 101 ..... 0111011 @r
+pm2sadd_hx 11010 10 ..... ..... 101 ..... 0111011 @r
+mul_w00 10000 11 ..... ..... 011 ..... 0111011 @r
+mul_w01 10010 11 ..... ..... 001 ..... 0111011 @r
+mul_w11 10010 11 ..... ..... 011 ..... 0111011 @r
+mulsu_w00 11100 11 ..... ..... 011 ..... 0111011 @r
+mulsu_w11 11110 11 ..... ..... 011 ..... 0111011 @r
+mulu_w00 10100 11 ..... ..... 011 ..... 0111011 @r
+mulu_w01 10110 11 ..... ..... 001 ..... 0111011 @r
+mulu_w11 10110 11 ..... ..... 011 ..... 0111011 @r
diff --git a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
index 486184eeaf3..7edea099d01 100644
--- a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
@@ -707,3 +707,66 @@ GEN_SIMD_TRANS_64_VXSAT(pnclipup_w)
GEN_SIMD_TRANS_R1(cls)
GEN_SIMD_TRANS_R1_64(clsw)
+/* Packed SIMD - Pure Multiplication Operations */
+GEN_SIMD_TRANS(pmulh_h)
+GEN_SIMD_TRANS(pmulhsu_h)
+GEN_SIMD_TRANS(pmulhu_h)
+GEN_SIMD_TRANS(pmulhr_h)
+GEN_SIMD_TRANS(pmulhrsu_h)
+GEN_SIMD_TRANS(pmulhru_h)
+GEN_SIMD_TRANS_64(pmulh_w)
+GEN_SIMD_TRANS_64(pmulhr_w)
+GEN_SIMD_TRANS_64(pmulhsu_w)
+GEN_SIMD_TRANS_64(pmulhrsu_w)
+GEN_SIMD_TRANS_64(pmulhu_w)
+GEN_SIMD_TRANS_64(pmulhru_w)
+GEN_SIMD_TRANS_32(mulhr)
+GEN_SIMD_TRANS_32(mulhrsu)
+GEN_SIMD_TRANS_32(mulhru)
+GEN_SIMD_TRANS(pmulh_h_b0)
+GEN_SIMD_TRANS(pmulh_h_b1)
+GEN_SIMD_TRANS(pmulhsu_h_b0)
+GEN_SIMD_TRANS(pmulhsu_h_b1)
+GEN_SIMD_TRANS_32(mulh_h0)
+GEN_SIMD_TRANS_32(mulh_h1)
+GEN_SIMD_TRANS_32(mulhsu_h0)
+GEN_SIMD_TRANS_32(mulhsu_h1)
+GEN_SIMD_TRANS_64(pmulh_w_h0)
+GEN_SIMD_TRANS_64(pmulh_w_h1)
+GEN_SIMD_TRANS_64(pmulhsu_w_h0)
+GEN_SIMD_TRANS_64(pmulhsu_w_h1)
+GEN_SIMD_TRANS(pmul_h_b00)
+GEN_SIMD_TRANS(pmul_h_b01)
+GEN_SIMD_TRANS(pmul_h_b11)
+GEN_SIMD_TRANS(pmulsu_h_b00)
+GEN_SIMD_TRANS(pmulsu_h_b11)
+GEN_SIMD_TRANS(pmulu_h_b00)
+GEN_SIMD_TRANS(pmulu_h_b01)
+GEN_SIMD_TRANS(pmulu_h_b11)
+GEN_SIMD_TRANS_64(pmul_w_h00)
+GEN_SIMD_TRANS_64(pmul_w_h01)
+GEN_SIMD_TRANS_64(pmul_w_h11)
+GEN_SIMD_TRANS_64(pmulsu_w_h00)
+GEN_SIMD_TRANS_64(pmulsu_w_h11)
+GEN_SIMD_TRANS_64(pmulu_w_h00)
+GEN_SIMD_TRANS_64(pmulu_w_h01)
+GEN_SIMD_TRANS_64(pmulu_w_h11)
+GEN_SIMD_TRANS_VXSAT(pm2sadd_h)
+GEN_SIMD_TRANS_VXSAT(pm2sadd_hx)
+GEN_SIMD_TRANS_32(mul_h00)
+GEN_SIMD_TRANS_32(mul_h01)
+GEN_SIMD_TRANS_32(mul_h11)
+GEN_SIMD_TRANS_32(mulsu_h00)
+GEN_SIMD_TRANS_32(mulsu_h11)
+GEN_SIMD_TRANS_32(mulu_h00)
+GEN_SIMD_TRANS_32(mulu_h01)
+GEN_SIMD_TRANS_32(mulu_h11)
+GEN_SIMD_TRANS_64(mul_w00)
+GEN_SIMD_TRANS_64(mul_w01)
+GEN_SIMD_TRANS_64(mul_w11)
+GEN_SIMD_TRANS_64(mulsu_w00)
+GEN_SIMD_TRANS_64(mulsu_w11)
+GEN_SIMD_TRANS_64(mulu_w00)
+GEN_SIMD_TRANS_64(mulu_w01)
+GEN_SIMD_TRANS_64(mulu_w11)
+
diff --git a/target/riscv/tcg/psimd_helper.c b/target/riscv/tcg/psimd_helper.c
index 99f11f084f2..5be8fe257f8 100644
--- a/target/riscv/tcg/psimd_helper.c
+++ b/target/riscv/tcg/psimd_helper.c
@@ -2259,3 +2259,187 @@ GEN_PSIMD_CLS(cls, target_ulong, uint32_t, clrsb32)
GEN_PSIMD_CLS(clsw, uint64_t, uint32_t, clrsb32)
+/* Pure multiplication operations */
+
+GEN_PSIMD_MUL_HIGH(pmulh_h, target_ulong, int16_t, int16_t, int32_t,
+ uint16_t, EXTRACT16, INSERT16, ELEMS_H, 16, 0,
+ PSIMD_MUL_S32)
+GEN_PSIMD_MUL_HIGH(pmulhsu_h, target_ulong, int16_t, uint16_t, int32_t,
+ uint16_t, EXTRACT16, INSERT16, ELEMS_H, 16, 0,
+ PSIMD_MUL_SU32)
+GEN_PSIMD_MUL_HIGH(pmulhu_h, target_ulong, uint16_t, uint16_t, uint32_t,
+ uint16_t, EXTRACT16, INSERT16, ELEMS_H, 16, 0,
+ PSIMD_MUL_U32)
+GEN_PSIMD_MUL_HIGH(pmulhr_h, target_ulong, int16_t, int16_t, int32_t,
+ uint16_t, EXTRACT16, INSERT16, ELEMS_H, 16, 1 << 15,
+ PSIMD_MUL_S32)
+GEN_PSIMD_MUL_HIGH(pmulhrsu_h, target_ulong, int16_t, uint16_t, int32_t,
+ uint16_t, EXTRACT16, INSERT16, ELEMS_H, 16, 1 << 15,
+ PSIMD_MUL_SU32)
+GEN_PSIMD_MUL_HIGH(pmulhru_h, target_ulong, uint16_t, uint16_t, uint32_t,
+ uint16_t, EXTRACT16, INSERT16, ELEMS_H, 16, 1 << 15,
+ PSIMD_MUL_U32)
+
+GEN_PSIMD_MUL_HIGH(pmulh_w, uint64_t, int32_t, int32_t, int64_t,
+ uint32_t, EXTRACT32, INSERT32, ELEMS_W, 32, 0,
+ PSIMD_MUL_S64)
+GEN_PSIMD_MUL_HIGH(pmulhr_w, uint64_t, int32_t, int32_t, int64_t,
+ uint32_t, EXTRACT32, INSERT32, ELEMS_W, 32, 1LL << 31,
+ PSIMD_MUL_S64)
+GEN_PSIMD_MUL_HIGH(pmulhsu_w, uint64_t, int32_t, uint32_t, int64_t,
+ uint32_t, EXTRACT32, INSERT32, ELEMS_W, 32, 0,
+ PSIMD_MUL_SU64)
+GEN_PSIMD_MUL_HIGH(pmulhrsu_w, uint64_t, int32_t, uint32_t, int64_t,
+ uint32_t, EXTRACT32, INSERT32, ELEMS_W, 32, 1LL << 31,
+ PSIMD_MUL_SU64)
+GEN_PSIMD_MUL_HIGH(pmulhu_w, uint64_t, uint32_t, uint32_t, uint64_t,
+ uint32_t, EXTRACT32, INSERT32, ELEMS_W, 32, 0,
+ PSIMD_MUL_U64)
+GEN_PSIMD_MUL_HIGH(pmulhru_w, uint64_t, uint32_t, uint32_t, uint64_t,
+ uint32_t, EXTRACT32, INSERT32, ELEMS_W, 32, 1LL << 31,
+ PSIMD_MUL_U64)
+
+GEN_PSIMD_MUL_HIGH(mulhr, uint32_t, int32_t, int32_t, int64_t,
+ uint32_t, EXTRACT32, INSERT32, ELEMS_W, 32, 1LL << 31,
+ PSIMD_MUL_S64)
+GEN_PSIMD_MUL_HIGH(mulhrsu, uint32_t, int32_t, uint32_t, int64_t,
+ uint32_t, EXTRACT32, INSERT32, ELEMS_W, 32, 1LL << 31,
+ PSIMD_MUL_SU64)
+GEN_PSIMD_MUL_HIGH(mulhru, uint32_t, uint32_t, uint32_t, uint64_t,
+ uint32_t, EXTRACT32, INSERT32, ELEMS_W, 32, 1LL << 31,
+ PSIMD_MUL_U64)
+
+GEN_PSIMD_MUL_HIGH_SEL(pmulh_h_b0, target_ulong, int16_t, int8_t,
+ int32_t, uint16_t, EXTRACT16, EXTRACT8, INSERT16,
+ ELEMS_H, 2, 0, 8, PSIMD_MUL_S32)
+GEN_PSIMD_MUL_HIGH_SEL(pmulh_h_b1, target_ulong, int16_t, int8_t,
+ int32_t, uint16_t, EXTRACT16, EXTRACT8, INSERT16,
+ ELEMS_H, 2, 1, 8, PSIMD_MUL_S32)
+GEN_PSIMD_MUL_HIGH_SEL(pmulhsu_h_b0, target_ulong, int16_t, uint8_t,
+ int32_t, uint16_t, EXTRACT16, EXTRACT8, INSERT16,
+ ELEMS_H, 2, 0, 8, PSIMD_MUL_SU32)
+GEN_PSIMD_MUL_HIGH_SEL(pmulhsu_h_b1, target_ulong, int16_t, uint8_t,
+ int32_t, uint16_t, EXTRACT16, EXTRACT8, INSERT16,
+ ELEMS_H, 2, 1, 8, PSIMD_MUL_SU32)
+
+GEN_PSIMD_MUL_HIGH_SEL(mulh_h0, uint32_t, int32_t, int16_t,
+ int64_t, uint32_t, EXTRACT32, EXTRACT16, INSERT32,
+ ELEMS_W, 0, 0, 16, PSIMD_MUL_S64)
+GEN_PSIMD_MUL_HIGH_SEL(mulh_h1, uint32_t, int32_t, int16_t,
+ int64_t, uint32_t, EXTRACT32, EXTRACT16, INSERT32,
+ ELEMS_W, 0, 1, 16, PSIMD_MUL_S64)
+GEN_PSIMD_MUL_HIGH_SEL(mulhsu_h0, uint32_t, int32_t, uint16_t,
+ int64_t, uint32_t, EXTRACT32, EXTRACT16, INSERT32,
+ ELEMS_W, 0, 0, 16, PSIMD_MUL_SU64)
+GEN_PSIMD_MUL_HIGH_SEL(mulhsu_h1, uint32_t, int32_t, uint16_t,
+ int64_t, uint32_t, EXTRACT32, EXTRACT16, INSERT32,
+ ELEMS_W, 0, 1, 16, PSIMD_MUL_SU64)
+
+GEN_PSIMD_MUL_HIGH_SEL(pmulh_w_h0, uint64_t, int32_t, int16_t,
+ int64_t, uint32_t, EXTRACT32, EXTRACT16, INSERT32,
+ ELEMS_W, 2, 0, 16, PSIMD_MUL_S64)
+GEN_PSIMD_MUL_HIGH_SEL(pmulh_w_h1, uint64_t, int32_t, int16_t,
+ int64_t, uint32_t, EXTRACT32, EXTRACT16, INSERT32,
+ ELEMS_W, 2, 1, 16, PSIMD_MUL_S64)
+GEN_PSIMD_MUL_HIGH_SEL(pmulhsu_w_h0, uint64_t, int32_t, uint16_t,
+ int64_t, uint32_t, EXTRACT32, EXTRACT16, INSERT32,
+ ELEMS_W, 2, 0, 16, PSIMD_MUL_SU64)
+GEN_PSIMD_MUL_HIGH_SEL(pmulhsu_w_h1, uint64_t, int32_t, uint16_t,
+ int64_t, uint32_t, EXTRACT32, EXTRACT16, INSERT32,
+ ELEMS_W, 2, 1, 16, PSIMD_MUL_SU64)
+
+GEN_PSIMD_MUL_ELEM_INDEXED(pmul_h_b00, target_ulong, int8_t, int8_t,
+ int16_t, uint16_t, EXTRACT8, INSERT16, ELEMS_H,
+ 2, 0, 0, PSIMD_MUL_S32)
+GEN_PSIMD_MUL_ELEM_INDEXED(pmul_h_b01, target_ulong, int8_t, int8_t,
+ int16_t, uint16_t, EXTRACT8, INSERT16, ELEMS_H,
+ 2, 0, 1, PSIMD_MUL_S32)
+GEN_PSIMD_MUL_ELEM_INDEXED(pmul_h_b11, target_ulong, int8_t, int8_t,
+ int16_t, uint16_t, EXTRACT8, INSERT16, ELEMS_H,
+ 2, 1, 1, PSIMD_MUL_S32)
+
+GEN_PSIMD_MUL_ELEM_INDEXED(pmulsu_h_b00, target_ulong, int8_t, uint8_t,
+ int16_t, uint16_t, EXTRACT8, INSERT16, ELEMS_H,
+ 2, 0, 0, PSIMD_MUL_SU16)
+GEN_PSIMD_MUL_ELEM_INDEXED(pmulsu_h_b11, target_ulong, int8_t, uint8_t,
+ int16_t, uint16_t, EXTRACT8, INSERT16, ELEMS_H,
+ 2, 1, 1, PSIMD_MUL_SU16)
+
+GEN_PSIMD_MUL_ELEM_INDEXED(pmulu_h_b00, target_ulong, uint8_t, uint8_t,
+ uint16_t, uint16_t, EXTRACT8, INSERT16, ELEMS_H,
+ 2, 0, 0, PSIMD_MUL_U32)
+GEN_PSIMD_MUL_ELEM_INDEXED(pmulu_h_b01, target_ulong, uint8_t, uint8_t,
+ uint16_t, uint16_t, EXTRACT8, INSERT16, ELEMS_H,
+ 2, 0, 1, PSIMD_MUL_U32)
+GEN_PSIMD_MUL_ELEM_INDEXED(pmulu_h_b11, target_ulong, uint8_t, uint8_t,
+ uint16_t, uint16_t, EXTRACT8, INSERT16, ELEMS_H,
+ 2, 1, 1, PSIMD_MUL_U32)
+
+GEN_PSIMD_MUL_ELEM_INDEXED(pmul_w_h00, uint64_t, int16_t, int16_t,
+ int32_t, uint32_t, EXTRACT16, INSERT32, ELEMS_W,
+ 2, 0, 0, PSIMD_MUL_S32)
+GEN_PSIMD_MUL_ELEM_INDEXED(pmul_w_h01, uint64_t, int16_t, int16_t,
+ int32_t, uint32_t, EXTRACT16, INSERT32, ELEMS_W,
+ 2, 0, 1, PSIMD_MUL_S32)
+GEN_PSIMD_MUL_ELEM_INDEXED(pmul_w_h11, uint64_t, int16_t, int16_t,
+ int32_t, uint32_t, EXTRACT16, INSERT32, ELEMS_W,
+ 2, 1, 1, PSIMD_MUL_S32)
+
+GEN_PSIMD_MUL_ELEM_INDEXED(pmulsu_w_h00, uint64_t, int16_t, uint16_t,
+ int32_t, uint32_t, EXTRACT16, INSERT32, ELEMS_W,
+ 2, 0, 0, PSIMD_MUL_SU32)
+GEN_PSIMD_MUL_ELEM_INDEXED(pmulsu_w_h11, uint64_t, int16_t, uint16_t,
+ int32_t, uint32_t, EXTRACT16, INSERT32, ELEMS_W,
+ 2, 1, 1, PSIMD_MUL_SU32)
+
+GEN_PSIMD_MUL_ELEM_INDEXED(pmulu_w_h00, uint64_t, uint16_t, uint16_t,
+ uint32_t, uint32_t, EXTRACT16, INSERT32, ELEMS_W,
+ 2, 0, 0, PSIMD_MUL_U32)
+GEN_PSIMD_MUL_ELEM_INDEXED(pmulu_w_h01, uint64_t, uint16_t, uint16_t,
+ uint32_t, uint32_t, EXTRACT16, INSERT32, ELEMS_W,
+ 2, 0, 1, PSIMD_MUL_U32)
+GEN_PSIMD_MUL_ELEM_INDEXED(pmulu_w_h11, uint64_t, uint16_t, uint16_t,
+ uint32_t, uint32_t, EXTRACT16, INSERT32, ELEMS_W,
+ 2, 1, 1, PSIMD_MUL_U32)
+
+GEN_PSIMD_2WAY_SAT_MUL(pm2sadd_h, 0, 1, 0, 1)
+GEN_PSIMD_2WAY_SAT_MUL(pm2sadd_hx, 0, 1, 1, 0)
+
+GEN_PSIMD_MUL_ELEM_SCALAR(mul_h00, uint32_t, int16_t, int16_t,
+ int32_t, EXTRACT16, 0, 0, PSIMD_MUL_S32)
+GEN_PSIMD_MUL_ELEM_SCALAR(mul_h01, uint32_t, int16_t, int16_t,
+ int32_t, EXTRACT16, 0, 1, PSIMD_MUL_S32)
+GEN_PSIMD_MUL_ELEM_SCALAR(mul_h11, uint32_t, int16_t, int16_t,
+ int32_t, EXTRACT16, 1, 1, PSIMD_MUL_S32)
+
+GEN_PSIMD_MUL_ELEM_SCALAR(mulsu_h00, uint32_t, int16_t, uint16_t,
+ int32_t, EXTRACT16, 0, 0, PSIMD_MUL_SU32)
+GEN_PSIMD_MUL_ELEM_SCALAR(mulsu_h11, uint32_t, int16_t, uint16_t,
+ int32_t, EXTRACT16, 1, 1, PSIMD_MUL_SU32)
+
+GEN_PSIMD_MUL_ELEM_SCALAR(mulu_h00, uint32_t, uint16_t, uint16_t,
+ uint32_t, EXTRACT16, 0, 0, PSIMD_MUL_U32)
+GEN_PSIMD_MUL_ELEM_SCALAR(mulu_h01, uint32_t, uint16_t, uint16_t,
+ uint32_t, EXTRACT16, 0, 1, PSIMD_MUL_U32)
+GEN_PSIMD_MUL_ELEM_SCALAR(mulu_h11, uint32_t, uint16_t, uint16_t,
+ uint32_t, EXTRACT16, 1, 1, PSIMD_MUL_U32)
+
+GEN_PSIMD_MUL_ELEM_SCALAR(mul_w00, uint64_t, int32_t, int32_t,
+ int64_t, EXTRACT32, 0, 0, PSIMD_MUL_S64)
+GEN_PSIMD_MUL_ELEM_SCALAR(mul_w01, uint64_t, int32_t, int32_t,
+ int64_t, EXTRACT32, 0, 1, PSIMD_MUL_S64)
+GEN_PSIMD_MUL_ELEM_SCALAR(mul_w11, uint64_t, int32_t, int32_t,
+ int64_t, EXTRACT32, 1, 1, PSIMD_MUL_S64)
+
+GEN_PSIMD_MUL_ELEM_SCALAR(mulsu_w00, uint64_t, int32_t, uint32_t,
+ int64_t, EXTRACT32, 0, 0, PSIMD_MUL_SU64)
+GEN_PSIMD_MUL_ELEM_SCALAR(mulsu_w11, uint64_t, int32_t, uint32_t,
+ int64_t, EXTRACT32, 1, 1, PSIMD_MUL_SU64)
+
+GEN_PSIMD_MUL_ELEM_SCALAR(mulu_w00, uint64_t, uint32_t, uint32_t,
+ uint64_t, EXTRACT32, 0, 0, PSIMD_MUL_U64)
+GEN_PSIMD_MUL_ELEM_SCALAR(mulu_w01, uint64_t, uint32_t, uint32_t,
+ uint64_t, EXTRACT32, 0, 1, PSIMD_MUL_U64)
+GEN_PSIMD_MUL_ELEM_SCALAR(mulu_w11, uint64_t, uint32_t, uint32_t,
+ uint64_t, EXTRACT32, 1, 1, PSIMD_MUL_U64)
+
--
2.34.1
