Signed-off-by: Molly Chen <[email protected]>
---
target/riscv/insn32.decode | 16 ++++++++++++++
target/riscv/tcg/insn_trans/trans_rvp.c.inc | 24 +++++++++++++++++++++
target/riscv/tcg/translate.c | 2 ++
3 files changed, 42 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8720fedb592..403e17e439d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -44,6 +44,10 @@
%imm_p_ui16 20:4
%imm_p_ui32 20:5
%imm_p_ui64 20:6
+%imm_p_l1 16:8
+%imm_p_l2 15:s1 16:9
+%imm_p_l3 15:s9 24:1 !function=ex_shift_6
+%imm_p_l4 15:s9 24:1 !function=ex_shift_22
# Argument sets:
&empty
@@ -53,6 +57,7 @@
&r rd rs1 rs2
&r2 rd rs1
&r2_s rs1 rs2
+&p_l imm rd
&s imm rs1 rs2
&u imm rd
&shift shamt rs1 rd
@@ -114,6 +119,10 @@
@p_ui16 ..... .... ... ..... ... ..... ....... &i imm=%imm_p_ui16 %rs1 %rd
@p_ui32 ..... .... ... ..... ... ..... ....... &i imm=%imm_p_ui32 %rs1 %rd
@p_ui64 ..... .... ... ..... ... ..... ....... &i imm=%imm_p_ui64 %rs1 %rd
+@p_l1 ........ ........ .... ..... ....... &p_l imm=%imm_p_l1 %rd
+@p_l2 ....... .......... ... ..... ....... &p_l imm=%imm_p_l2 %rd
+@p_l3 ....... .......... ... ..... ....... &p_l imm=%imm_p_l3 %rd
+@p_l4 ....... .......... ... ..... ....... &p_l imm=%imm_p_l4 %rd
# Formats 64:
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1
%rd
@@ -1614,3 +1623,10 @@ pm4addu_h 10100 11 ..... ..... 101 ..... 0111011 @r
pm4adda_h 10001 11 ..... ..... 101 ..... 0111011 @r
pm4addasu_h 11101 11 ..... ..... 101 ..... 0111011 @r
pm4addau_h 10101 11 ..... ..... 101 ..... 0111011 @r
+
+# Packed SIMD - Load and Replicate instructions
+pli_b 10110100 ........ 0010 ..... 0011011 @p_l1
+pli_h 1011000 .......... 010 ..... 0011011 @p_l2
+plui_h 1111000 .......... 010 ..... 0011011 @p_l3
+pli_w 1011001 ..... ..... 010 ..... 0011011 @p_l2
+plui_w 1111001 ..... ..... 010 ..... 0011011 @p_l4
diff --git a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
index 6c344a66dc8..4d5fc230d2e 100644
--- a/target/riscv/tcg/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvp.c.inc
@@ -902,3 +902,27 @@ GEN_SIMD_TRANS_ACC_64(pm4adda_h)
GEN_SIMD_TRANS_ACC_64(pm4addasu_h)
GEN_SIMD_TRANS_ACC_64(pm4addau_h)
+#define GEN_PLI(NAME, PRE_REQ, IMM_TYPE, LIMIT, SHIFT, ADDEND) \
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
+{ \
+ PRE_REQ \
+ REQUIRE_RVP(ctx); \
+ int i = 1; \
+ IMM_TYPE imm = a->imm; \
+ while (i < (LIMIT)) { \
+ imm = (imm << (SHIFT)) + (ADDEND); \
+ i++; \
+ } \
+ gen_set_gpri(ctx, a->rd, imm); \
+ return true; \
+}
+
+GEN_PLI(pli_b, , target_long, TARGET_LONG_SIZE, 8, a->imm)
+GEN_PLI(pli_h, , target_long, TARGET_LONG_SIZE / 2, 16,
+ a->imm & 0xFFFF)
+GEN_PLI(plui_h, , target_long, TARGET_LONG_SIZE / 2, 16,
+ a->imm & 0xFFFF)
+GEN_PLI(pli_w, REQUIRE_64BIT(ctx); , int64_t, TARGET_LONG_SIZE / 4, 32,
+ a->imm & 0xFFFFFFFF)
+GEN_PLI(plui_w, REQUIRE_64BIT(ctx); , int64_t, TARGET_LONG_SIZE / 4, 32,
+ a->imm & 0xFFFFFFFF)
diff --git a/target/riscv/tcg/translate.c b/target/riscv/tcg/translate.c
index 0df9d4190f1..668ec3120af 100644
--- a/target/riscv/tcg/translate.c
+++ b/target/riscv/tcg/translate.c
@@ -790,7 +790,9 @@ EX_SH(1)
EX_SH(2)
EX_SH(3)
EX_SH(4)
+EX_SH(6)
EX_SH(12)
+EX_SH(22)
#define REQUIRE_EXT(ctx, ext) do { \
if (!has_ext(ctx, ext)) { \
--
2.34.1
