On 2026/08/26 10:38 AM, Chinmay Rath wrote: > From: "Mukesh Kumar Chaurasiya (IBM)" <[email protected]> > > Instruction converted: > > - sraw > - srawi
This doesn't give the idea on what is being done - could have been more explicit that the insns are being moved to decode tree spec. But its upto you. > > Signed-off-by: Mukesh Kumar Chaurasiya (IBM) <[email protected]> > Reviewed-by: Glenn Miles <[email protected]> > Signed-off-by: Chinmay Rath <[email protected]> > --- > target/ppc/helper.h | 2 +- > target/ppc/insn32.decode | 6 ++-- > target/ppc/int_helper.c | 2 +- > target/ppc/translate.c | 42 ---------------------- > target/ppc/translate/fixedpoint-impl.c.inc | 41 +++++++++++++++++++++ > 5 files changed, 47 insertions(+), 46 deletions(-) > > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index 6df3de6516..3aff559504 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -64,7 +64,7 @@ DEF_HELPER_4(DIVWE, tl, env, tl, tl, i32) > > DEF_HELPER_FLAGS_1(POPCNTB, TCG_CALL_NO_RWG_SE, tl, tl) > DEF_HELPER_FLAGS_2(CMPB, TCG_CALL_NO_RWG_SE, tl, tl, tl) > -DEF_HELPER_3(sraw, tl, env, tl, tl) > +DEF_HELPER_3(SRAW, tl, env, tl, tl) > DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64) > DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64) > DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64) > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index 66d2f455a9..af35a44223 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -507,8 +507,10 @@ HASHCHKP 011111 ..... ..... ..... 1010110010 . > @X_DW > > # Fixed-Point Shift Instructions > > -SLW 011111 ..... ..... ..... 0000011000 . @X_rc > -SRW 011111 ..... ..... ..... 1000011000 . @X_rc > +SLW 011111 ..... ..... ..... 0000011000 . @X_rc > +SRAW 011111 ..... ..... ..... 1100011000 . @X_rc > +SRAWI 011111 ..... ..... ..... 1100111000 . @X_rc > +SRW 011111 ..... ..... ..... 1000011000 . @X_rc > > Nit: extra blank line can be removed. Otherwise, the changes look good to me. Reviewed-by: Amit Machhiwal <[email protected]> > ## BCD Assist > diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c > index dc55ccadf7..b161f930ec 100644 > --- a/target/ppc/int_helper.c > +++ b/target/ppc/int_helper.c > @@ -235,7 +235,7 @@ target_ulong helper_CMPB(target_ulong rs, target_ulong rb) > } > > /* shift right arithmetic helper */ > -target_ulong helper_sraw(CPUPPCState *env, target_ulong value, > +target_ulong helper_SRAW(CPUPPCState *env, target_ulong value, > target_ulong shift) > { > int32_t ret; > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index f2b7505634..f00071aa91 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -2316,46 +2316,6 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06); > /*** Integer shift > ***/ > > > -/* sraw & sraw. */ > -static void gen_sraw(DisasContext *ctx) > -{ > - gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env, > - cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); > - if (unlikely(Rc(ctx->opcode) != 0)) { > - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); > - } > -} > - > -/* srawi & srawi. */ > -static void gen_srawi(DisasContext *ctx) > -{ > - int sh = SH(ctx->opcode); > - TCGv dst = cpu_gpr[rA(ctx->opcode)]; > - TCGv src = cpu_gpr[rS(ctx->opcode)]; > - if (sh == 0) { > - tcg_gen_ext32s_tl(dst, src); > - tcg_gen_movi_tl(cpu_ca, 0); > - if (is_isa300(ctx)) { > - tcg_gen_movi_tl(cpu_ca32, 0); > - } > - } else { > - TCGv t0; > - tcg_gen_ext32s_tl(dst, src); > - tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); > - t0 = tcg_temp_new(); > - tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); > - tcg_gen_and_tl(cpu_ca, cpu_ca, t0); > - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); > - if (is_isa300(ctx)) { > - tcg_gen_mov_tl(cpu_ca32, cpu_ca); > - } > - tcg_gen_sari_tl(dst, dst, sh); > - } > - if (unlikely(Rc(ctx->opcode) != 0)) { > - gen_set_Rc0(ctx, dst); > - } > -} > - > #if defined(TARGET_PPC64) > /* sld & sld. */ > static void gen_sld(DisasContext *ctx) > @@ -5730,8 +5690,6 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, > PPC_NONE, PPC2_ISA300), > GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), > GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), > GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), > -GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), > -GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), > #if defined(TARGET_PPC64) > GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), > GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), > diff --git a/target/ppc/translate/fixedpoint-impl.c.inc > b/target/ppc/translate/fixedpoint-impl.c.inc > index 9d04b96316..234404e459 100644 > --- a/target/ppc/translate/fixedpoint-impl.c.inc > +++ b/target/ppc/translate/fixedpoint-impl.c.inc > @@ -1454,3 +1454,44 @@ static bool trans_SRW(DisasContext *ctx, arg_SRW *a) > } > return true; > } > + > +/* sraw & sraw. */ > +static bool trans_SRAW(DisasContext *ctx, arg_SRAW *a) > +{ > + gen_helper_SRAW(cpu_gpr[a->ra], tcg_env, > + cpu_gpr[a->rt], cpu_gpr[a->rb]); > + if (unlikely(a->rc)) { > + gen_set_Rc0(ctx, cpu_gpr[a->ra]); > + } > + return true; > +} > + > +/* srawi & srawi. */ > +static bool trans_SRAWI(DisasContext *ctx, arg_SRAWI *a) > +{ > + TCGv dst = cpu_gpr[a->ra]; > + TCGv src = cpu_gpr[a->rt]; > + if (a->rb == 0) { > + tcg_gen_ext32s_tl(dst, src); > + tcg_gen_movi_tl(cpu_ca, 0); > + if (is_isa300(ctx)) { > + tcg_gen_movi_tl(cpu_ca32, 0); > + } > + } else { > + TCGv t0; > + tcg_gen_ext32s_tl(dst, src); > + tcg_gen_andi_tl(cpu_ca, dst, (1ULL << a->rb) - 1); > + t0 = tcg_temp_new(); > + tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); > + tcg_gen_and_tl(cpu_ca, cpu_ca, t0); > + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); > + if (is_isa300(ctx)) { > + tcg_gen_mov_tl(cpu_ca32, cpu_ca); > + } > + tcg_gen_sari_tl(dst, dst, a->rb); > + } > + if (unlikely(a->rc)) { > + gen_set_Rc0(ctx, dst); > + } > + return true; > +} > -- > 2.55.0 >
