Signed-off-by: Mingliang Liu <[email protected]>
---
disas/riscv-op.c.inc | 3 ++-
disas/riscv.c | 6 ++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
index 07b56f5d52..425473ee61 100644
--- a/disas/riscv-op.c.inc
+++ b/disas/riscv-op.c.inc
@@ -491,9 +491,10 @@ OP(vaadd_vx, "vaadd.vx", rv_codec_v_r,
rv_fmt_vd_vs2_rs1_vm)
OP(vaaddu_vv, "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vaaddu_vx, "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
OP(vabd_vv, "vabd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
-OP(vabd_vx, "vabd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vabd_vx, "vabd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, rvcp_vabd_vx)
OP(vabdu_vv, "vabdu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
OP(vabdu_vx, "vabdu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
+OP(vabs_v, "vabs.v", rv_codec_illegal, rv_fmt_vd_vs2_vm)
OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
diff --git a/disas/riscv.c b/disas/riscv.c
index e0a8b3a756..2aecaaa25a 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -103,6 +103,7 @@ static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0,
rvc_end };
static const rvc_constraint rvcc_ret[] = { rvc_rs1_eq_ra, rvc_end };
static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
rvc_end };
+static const rvc_constraint rvcc_vabs_v[] = { rvc_rs1_eq_x0, rvc_end };
static const rvc_constraint rvcc_true[] = { rvc_end };
/* pseudo-instruction metadata */
@@ -242,6 +243,11 @@ static const rv_comp_data rvcp_fsgnjx_q[] = {
{ },
};
+static const rv_comp_data rvcp_vabd_vx[] = {
+ { &op_vabs_v, rvcc_vabs_v },
+ { },
+};
+
/* Convert compressed insns into normal insns via pseudo expansion. */
#define DECOMP(X) &(const rv_comp_data){ &X, rvcc_true }
--
2.39.5
