On Mon, 14 Sept 2026 at 20:24, Gilles Grimaud <[email protected]> wrote: > > Armv6-M supports no more than 32 external interrupts. Its ICTR and Active > Bit Register locations are reserved, and Cortex-M0 implements two priority > bits. > > Reject Armv6-M NVIC configurations with more than 32 external interrupts. > Add a check-tcg test that verifies the reserved register behavior and > priority masking on the microbit machine. > > Signed-off-by: Gilles Grimaud <[email protected]>
Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
