Keep the existing mask (0x173f) for CPUs with ARM_FEATURE_V7, and use a mask that excludes TEX (0x1707) for Armv6-M. PMSAv8 is handled by the earlier branch and is unaffected by this change.
After writing MPU_RASR on an Armv6-M CPU a subsequent read returns zero for the TEX bits; Armv7-M behaviour remains unchanged. Suggested-by: Peter Maydell <[email protected]> Signed-off-by: Gilles Grimaud <[email protected]> --- hw/intc/armv7m_nvic.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 51d3dba852..4136c91f23 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1996,7 +1996,12 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } cpu->env.pmsav7.drsr[region] = value & 0xff3f; - cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f; + if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { + cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f; + } else { + /* Armv6-M has XN, AP, S, C and B, but no TEX field. */ + cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x1707; + } tlb_flush(CPU(cpu)); break; } -- 2.55.0
