On Mon, 14 Sept 2026 at 20:26, Gilles Grimaud <[email protected]> wrote: > > The alias registers MPU_RBAR_A1-A3 and MPU_RASR_A1-A3 (v7M) or > MPU_RLAR_A1-A3 (v8M) exist only when the Main Extension is implemented > (ARM_FEATURE_M_MAIN). The current NVIC decoder groups the principal > register and its aliases in the same case fall-through, so once the > PMSAv7 path is enabled for v6-M (or the PMSAv8 path for v8-M Baseline) > the aliases become incorrectly accessible. > > The fix reorders the case statements for the four locations (read and > write of RBAR and RASR/RLAR) in hw/intc/armv7m_nvic.c. Alias cases are > placed before the principal register case with a fall-through and are > guarded by a test of ARM_FEATURE_M_MAIN. If the Main Extension is absent > the code jumps to bad_offset, causing a read to log "NVIC: Bad read > offset" and return zero, and a write to log "NVIC: Bad write offset" and > be ignored. The principal MPU_RBAR and MPU_RASR/RLAR registers remain > functional for CPUs that implement the corresponding MPU. > > Suggested-by: Peter Maydell <[email protected]> > Signed-off-by: Gilles Grimaud <[email protected]> > ---
Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
