On Mon, 14 Sept 2026 at 20:27, Gilles Grimaud <[email protected]> wrote: > > Keep the existing mask (0x173f) for CPUs with ARM_FEATURE_V7, and use a > mask that excludes TEX (0x1707) for Armv6-M. PMSAv8 is handled by the > earlier branch and is unaffected by this change. > > After writing MPU_RASR on an Armv6-M CPU a subsequent read returns zero > for the TEX bits; Armv7-M behaviour remains unchanged. > > Suggested-by: Peter Maydell <[email protected]> > Signed-off-by: Gilles Grimaud <[email protected]>
Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
