On Mon, 14 Sept 2026 at 20:23, Gilles Grimaud <[email protected]> wrote: > > This RFC series refines the Armv6-M support in QEMU by correcting NVIC > limits, modelling the optional Cortex-M0+ privilege extension, > tightening MPU register access, fixing MPU region size checks, masking > TEX bits for Armv6-M, and reusing QEMU's existing PMSAv7 implementation > for the compatible v6-M MPU.
> Gilles Grimaud (6): > target/arm: enforce Armv6-M NVIC limits > target/arm: model Cortex-M0+ privilege extension > target/arm: MPU - limit regs RBAR/RASR A1-A3 to Main Extension > target/arm: MPU_RASR: mask TEX bits for Armv6-M > target/arm: fix MPU SIZE min for v6-M/v7-M/v7-R > target/arm: extend PMSAv7 support to v6-M CPUs I had some comments on patch 2, but patches 1 and 3-6 are fine and 3-6 don't depend on patch 2, so I've taken 1, 3-6 into target-arm.next. I plan to do a pullreq later today so those should appear upstream soon. thanks -- PMM
