On Wed, Oct 7, 2026 at 4:31 PM Bin Meng <[email protected]> wrote: > > This series corrects SPR access, cache configuration and instruction > availability in the Freescale Book E CPU models. It also adds system > TCG tests for e500mc, e5500 and e6500. > > The patches are grouped as follows: > > - patch #1-#4, bug fixes to PIR write access, the MAS5 SPR number and > cache block/line sizes (qemu-stable cc'ed) > - patch #5-#6, complete e500mc/e5500 L1 cache configuration and > remove redundant e6500 cache geometry bits > - patch #7-#11, register the missing cache, MMU-assist and sevearl > control SPRs > - patch #12-#14, split the PowerISA 2.05 instructions to several sub-flags > controlled groups, due to differences seen on the e500 series cores > - patch #15-#17: Add TCG tests for illegal-instruction exceptions, byte > comparison and parity results, and FPSCR field-mask handling >
Ping for review?
