On Tue, 6 Oct 2026, Bin Meng wrote:
The e500mc and e5500 core manuals define L2CFG0 as read-only SPR 519
(0x207) and L2CSR1 as writable SPR 1018 (0x3fa). U-Boot reads the
former to discover the private L2 cache and programs the latter to
select its stash ID. Missing registrations leave cache discovery
and stash setup incomplete.
Expose both registers on e500mc and e5500. Use the 128 KiB L2 geometry
specified by the e500mc manual and a 256 KiB default for e5500,
matching T1040/T1024. Other SoC integrations can override the capacity.
Note the e6500 shared L2 uses memory-mapped registers, hence we do not
add these SPRs to that core.
Reference:
- E500MCRM (Rev.3), section 2.15.1 and 2.15.3
https://www.nxp.com/docs/en/reference-manual/E500MCRM.pdf
- E5500RM (Rev.4), section 2.15.1 and 2.15.3
https://www.nxp.com/webapp/Download?colCode=E5500RM
- E6500RM (Rev.0), section 2.12.1 and 2.12.3
https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf
Signed-off-by: Bin Meng <[email protected]>
---
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c | 14 ++++++++++++++
2 files changed, 16 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index d3f1c82730..498b505a96 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1976,6 +1976,7 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define SPR_Exxx_L1CFG0 (0x203)
#define SPR_Exxx_L1CFG1 (0x204)
#define SPR_Exxx_NPIDR (0x205)
+#define SPR_Exxx_L2CFG0 (0x207)
I see there are more of these already. Disregard previous comment in that
case.
Regards,
BALATON Zoltan
#define SPR_ATBL (0x20E)
#define SPR_ATBU (0x20F)
#define SPR_IBAT0U (0x210)
@@ -2341,6 +2342,7 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define SPR_750_TDCH (0x3FA)
#define SPR_IABR2 (0x3FA)
#define SPR_40x_DCCR (0x3FA)
+#define SPR_Exxx_L2CSR1 (0x3FA)
#define SPR_ICTC (0x3FB)
#define SPR_40x_ICCR (0x3FB)
#define SPR_THRM1 (0x3FC)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index e5856b5b1d..21c6012fa1 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2974,6 +2974,20 @@ static void init_proc_e500(CPUPPCState *env, int version)
&spr_read_generic, &spr_write_e500_l2csr0,
0x00000000);
}
+ if (version == fsl_e500mc || version == fsl_e5500) {
+ /*
+ * L2CSIZE is in 64 KiB units. Use 128 KiB for e500mc and a
+ * 256 KiB default for e5500, matching the T1040/T1024 SoCs.
+ * Other SoC models can override the e5500 capacity.
+ */
+ spr_register(env, SPR_Exxx_L2CFG0, "L2CFG0",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ version == fsl_e500mc ? 0x3cb1c002 : 0x3cb1c004);
+ spr_register(env, SPR_Exxx_L2CSR1, "L2CSR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic32, 0);
+ }
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
